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RISC-V Offers Simple, Modular ISA
- erichocean 11y agoIf you're at all interesting in getting into hardware, buy yourself a cheap FPGA and put a RISC-V CPU on it. I'm doing it with my kids and it's been tons of fun. :)
- blackguardx 11y agoI recommend the DE0-Nano: https://www.adafruit.com/product/451 https://www.adafruit.com/product/451 Altera's tools are much nicer for the beginner to use than ones offered by Xilinx. This board also has a lot of peripherals you can interface with (ADC, accelerometer, etc.) to grow your skills.
- drakenot 11y agoWhat would be a use case for using one of these FPGAs rather than something like a Raspberry Pi with a traditional microcontroller? I'm genuinely interested. I've been really curious about FPGAs but I don't know what a good use case there is for them for a hobbyist.
- Ericson2314 11y agoFPGAs are for pretending you have the money to fab every hardware design iteration. Small CPUs are...not? Honestly the FPGA in data center stuff is probably mostly hype for most people, but toying with an FPGA is super fun.
- Ericson2314 11y agoTo see the board running your program, there's a rare beautiful moment where YOU, one hobbiest, designed the whole stack :).
- copperx 11y agoI don't know if this is a stupid question, but could one design a very basic LISP machine on a FPGA? how about a diminutive JVM?
- Redoubts 11y agoWhy not? It was done on real hardware in the 80s, right? hell, here's one: http://www.aviduratas.de/lisp/lispmfpga/ http://www.aviduratas.de/lisp/lispmfpga/
- FullyFunctional 11y agoIt's very easy. Personally, I find Reduceron [0,1] far more interesting. [0] https://www.cs.york.ac.uk/fp/reduceron/ https://www.cs.york.ac.uk/fp/reduceron/ [1] https://github.com/reduceron/Reduceron https://github.com/reduceron/Reduceron
- danellis 11y agoA few ARM CPUs have not a JVM, but the ability to accelerate a JVM by directly executing Java bytecode (Jazelle DBX). "The Jazelle extension uses low-level binary translation, implemented as an extra stage between the fetch and decode stages in the processor instruction pipeline. Recognised bytecodes are converted into a string of one or more native ARM instructions."
- jeffbush 11y agoI made a little FPGA LISP machine: https://github.com/jbush001/LispMicrocontroller https://github.com/jbush001/LispMicrocontroller
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- redtuesday 11y agoCool, haven't thought about that. I probably need to get an FPGA. Really liked the book "The Elements of Computing Systems" [1][2] in which one builds a computer from NAND gates upwards, a compiler, vm and finally a simple OS with applications. The hardware part of the course seems to be on coursera now as well. [3] [1] https://mitpress.mit.edu/books/elements-computing-systems https://mitpress.mit.edu/books/elements-computing-systems [2] http://www.nand2tetris.org/ http://www.nand2tetris.org/ [3] https://www.coursera.org/learn/build-a-computer https://www.coursera.org/learn/build-a-computer
- blackguardx 11y agoThe use case for these boards is to learn how to use FPGAs. Why would you use an FPGA? Mainly when you have specialized requirements that can't be met by processors. FPGAs mainly excel in parallelization. A designer can instantiate many copies of a circuit element like a processor or some dedicated hardware function and achieve higher throughput than with a normal processor. If your application doesn't require that, you might like them for the massive number of flexible I/O pins they offer. Lastly, using FPGAs as a hobby is rewarding just like any other hobby. Contrary to popular belief, you don't "program" with a programming language like with a processor. You describe the circuit functionality in a hardware description language and a synthesizer figures out how to map it to digital logic components. You get a better insight into how digital hardware works and how digital chips are designed. When you use them as a hobby, you get the feeling that you are designing a custom chip for whatever project you are working on. Indeed, FPGAs are routinely used to prototype digital chips.
- javajosh 11y agoSounds like something that might be just as enjoyable on a simulator.
- tremon 11y agoNo, not really. FPGA's by definition are massively parallel. There is no way you can simulate them on CPU's with any reasonable speed (think: 1ms cpu time for simulating one clock cycle, so your simulation maxes out at a few kHz max). That sucks all the enjoyment out of it.
- viraptor 11y agoWell... if you're going for something stupidly small/underpowered (ATTiny level of power consumption), but run out of cycles to handle multiple I/Os at the same time, FPGA allows you to cheat a little bit by doing things in parallel. For example with 10 inputs on standard CPUs you have to spend some cycles checking each one separately. With FPGAs you can have block for each and just get a signal propagated when something "interesting" actually happens. Then again, you could just invest in bigger batteries and better CPU instead :)
- FullyFunctional 11y agoHa! I often find myself wishing I had an FPGA. It's very common that I have to control external devices that would be straight forward with logic but requires all soft of hacks and tricks using a microcontroller. Here's just one simple example: controlling servos. Sure you can do that with most uC simply enough, say using timer interrupts, but what if I need to control 100 of them? In logic, I can just instantiate 100 very trivial pulse controllers where as this typically is impossible with a microcontroller or at the very least leaves no cycles free for any computation. Another example: you want to implement a nice little crypto, like ChaCha20. Even though ChaCha20 is efficient, it's still a lot of cycles for a microprocessor, where as an FPGA can implement this is a nice pipeline, potentially reaching speeds like 800 MB/s, while still having ample resources left for other work. I could go on.
- nickpsecurity 11y agoGreat comment and examples. The CPU's are optimized to try to do everything kind of fast a step at a time within specific constraints, often legacy. The FPGA's let us build just the right hardware for our computations using components that run in parallel with fewer constraints. The result is often some amazing performance/circuitry ratios.
- vvanders 11y agoTry interfacing one of them with DRAM, at a moderate speed. You'll learn: Pipelines, Caches, Why cache misses are so painful and a whole host of CPU performance stuff that "looks" esoteric will become plain as day.
- Cieplak 11y agoHave you tried Vivado? Xilinx ISE is hands down terrible, but supposedly Vivado was "500 man-years of engineering effort" [1]. Unfortunately, vendor lock-in means I can't try Altera's tools for my boards, but Vivado's high level synthesis is really cool. It generates a hardware design from a given C program, and then let's you tune the generated verilog [2]. [1]: http://www.eejournal.com/archives/articles/20120501-bigdeal http://www.eejournal.com/archives/articles/20120501-bigdeal [2]: http://xillybus.com/tutorials/vivado-hls-c-fpga-howto-1 http://xillybus.com/tutorials/vivado-hls-c-fpga-howto-1
- JamilD 11y agoVivado is miles ahead of Quartus, especially for beginners. Altera's tools have a very steep learning curve for beginners to hardware.
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- blackguardx 11y agoI think that is mainly a matter of opinion. Unfortunately, you can't use Vivado with Xilinx's older, cheaper chips. I think beginners are more likely to use these chips than their more advanced, expensive chips. We'll have to see if the Spartan-7 is supported by Vivado or not.
- asb 11y agoThe newish Arty board has a 7-series part and is only $99
- blackguardx 11y agoI've been wanting to try it, but for some reason Xilinx refuses to offer support for the Spartan-6. They only offer support for their expensive chips.
- ShinyCyril 11y agoI haven't checked out the high-level synthesis part, but I've been using Vivado for a project recently and it's absolutely horrible. To name some of the issues I've had; - Memory leaks (grows from about 1GB to 11GB and starts swapping in a couple of minutes when editing existing IP) - Single-threaded synthesis is slow (though isn't limited to Vivado specifically) - Failing after 20 minutes of synthesis because of errors that would be easy to check at the start - Placing debug cores can result in needing to synthesise, find something went wrong, delete debug core, re-synthesise, re-add debug nets, synthesise again... - Aggressive caching results in it trying to find nets which were changed and no longer exist, despite re-creating the IP in question from scratch - Vivado creates a ridiculous amount of temporary files and is a royal pain to use with version control (there is an entire document which details the methods to use if you want to create a project to be stored under version control) I've been playing around with IceStorm for the iCE40 device and it's an absolute joy to use: fast, stable and simple. I appreciate that there are a lot of complex tools and reports which Vivado provides, but I would much rather use an open source tool like IceStorm for synthesis alongside the advanced tools from Vivado.
- erichocean 11y agoAnd here's an FPGA optimized RISC-V RV32IM core for that device (Altera Cyclone IV): https://github.com/VectorBlox/orca https://github.com/VectorBlox/orca I haven't tried this particular one.
- vanjoe 11y agoI'm the principle author, I can answer any questions
- mdda 11y agoThis seems like an ultra-basic question (sorry). On the VectorBlox/orca github page, it mentions that the core takes ~2,000 LUT4s. Are those numbers apples-to-apples with the 22,320 LEs given for the Cyclone IV board mentioned earlier[1]? If so, then (naively) could one pack ~10 on that single FPGA? Or does the 'packing overhead' become a big problem? Or does the design use more (say) multiply units pro-rata, so that they become the limiting factor? [1] https://www.adafruit.com/product/451 https://www.adafruit.com/product/451
- bengesoff 11y agoI haven't simulated this to check but it may be the case that IO pins become a limiting factor. The Cyclone IV has 153 IO pins so the design would have to use less than ~15 to be able to fit 10 copies on.
- Dylan16807 11y agoWell a CPU doesn't inherently use any I/O pins so that shouldn't be a problem. You can easily add some logic to let CPUs share pins, too.
- bengesoff 11y agoGood point sir
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- FilthyAnalyst 11y agoThere is an amazing Amiga accelerator using the Alter FPGA http://www.kipper2k.com/accel600.html http://www.kipper2k.com/accel600.html
- dyselon 11y agoThe DE0-CV is a bit more expensive, but I think it's probably better than the Nano for the FPGA 101 type experiments. It's got more on the way of switches and LEDs, and the buttons are a lot easier to get to. I have both, and I had a lot more fun with low level learning activities with the CV than the Nano. Moving past that, I also enjoyed messing with the VGA and SD card peripherals more than the ADC and accelerometer, and also found those easier to add on after the fact.
- blackguardx 11y agoI added a hand-made VGA "shield" to the Nano and used 3 digital I/O pins to get 3 bit color. I don't have a picture of the add-on board handy, but you can see a breakout game I made here: http://jrward.org/breakout.html http://jrward.org/breakout.html
- dyselon 11y agoI also made a VGA shield for my Nano! I got a couple pictures at https://mobile.twitter.com/dyselon/status/648020130471899136 https://mobile.twitter.com/dyselon/status/648020130471899136 That project is actually kind of what convinced me to go ahead and buy the CV. It was fun, but it just felt like a lot of work making things that I could just already have on the board.
- vmorgulis 11y agoWhich CPU did you try?
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- dang 11y agoCan you tell us more about what you're doing and how? This seems like the kind of story HN would eat up, if you might like to write about it.
- razer6 11y agoYou may want to try PULPino: http://www.pulp-platform.org/ http://www.pulp-platform.org/
- tremon 11y agoAny FPGA's available yet with an open(ish) toolchain? Including the bitstream generator/programmer?
- IshKebab 11y agoI think some people had a full open source toolchain (or were close to it) for some of the Lattice FPGAs, but I think only the really feeble ones that have 10s of LUTs.
- badsock 11y agoYes, there's a fully open stack for the Lattice iCE40s (the largest of which has 7680 LUTs): http://www.clifford.at/yosys/ http://www.clifford.at/yosys/ (Verilog synthesis) https://github.com/cseed/arachne-pnr https://github.com/cseed/arachne-pnr (Place and route) http://www.clifford.at/icestorm/ http://www.clifford.at/icestorm/ (Bitstream generator and programmer)
- vmorgulis 11y agoI've just found their online simulator (caller ANGEL). It boots linux and busybox: http://riscv.org/angel-simulator/ http://riscv.org/angel-simulator/
- _kst_ 11y ago/ # uname -n ucbvax / # cat /proc/cpuinfo CPU info: PUNT! / # Amusing.
- AceJohnny2 11y agoSimple Memory Model The RISC-V address space is byte addressed and little-endian. Even though most other ISAs such as x86 and ARM have severalpotentially complex addressing modes, RISC-V only uses base+offset addressing with a 12-bit immediate to simplify load-store units. I remember reading [1] that one reason C became so popular was because it was easy to write a compiler for, not because it was easy to write a program in. Thus, compilers emerged for various platforms, making it accessible. At the opposite, stuff like Smalltalk (I may be mistaking the language) were complicated to implement and the compilers/environments were expensive, limiting the reach. Looks like the RISC-V is taking a page from this strategy book. [1] was it Gabriel's Worse Is Better essay? https://www.dreamsongs.com/RiseOfWorseIsBetter.html https://www.dreamsongs.com/RiseOfWorseIsBetter.html
- FullyFunctional 11y agoThat has no basis in reality. Smalltalk is to implement that one implementation fits in the Smalltalk-80 book. C got popular because it allowed low-level code to be implemented in something higher-level than assembler and moderately portably too (machines back then where as lot more dissimilar than today). It's hard to disassociate C from Unix, the former making the latter easy to port. A symbiotic relationship. It's important to remember C was designed for the processors of the time, whereas processors of today (RISC-V included) are arguebly primarily machines to run C. C has brought a lot of good but also a lot of bad that we are still dealing with: unchecked integer overflows, buffer under- and overflow, and more general memory corruption. No ISA since the SPARC even tries to offer support for non-C semantics.
- nickpsecurity 11y ago" C has brought a lot of good" I've seen no evidence that C brought us anything good. Anything I can do with C I can do with a Modula-2-like language with better safety and compiler robustness. If a check is a problem, I can disable it but it's there by default. Nonetheless, I'll look into any benefits you think C brought us that alternatives wouldn't have done.
- ashitlerferad 11y agoDirect link to the PDF: http://riscv.org/wp-content/uploads/2016/04/RISC-V-Offers-Simple-Modular-ISA.pdf http://riscv.org/wp-content/uploads/2016/04/RISC-V-Offers-Si...
- ashitlerferad 11y agoNo RISC-V post would be complete without a link to lowRISC: http://www.lowrisc.org/ http://www.lowrisc.org/
- maaku 11y agoThere are many other, equally if not more interesting implementations...
- ashitlerferad 11y agolowRISC is the only project that aims to distribute ASICs AFAIK. Are there others?
- reportingsjr 11y agoThe pulp platform has taped out a RISC-V based microcontroller, but I don't think they have plans to sell/really distribute any asics unfortunately.
- ashitlerferad 11y agoYeah, that is the problem with niche CPU arches; if mass quantities aren't available to buy (either lone chips or in consumer products), people aren't going to use it much. Not everyone can afford to have their own fab :)
- razer6 11y agoYou can always start playing around with PULPino on a FPGA :)
- maaku 11y agoPretty much everyone is looking at eventual ASIC fabrication. It just takes a lot of money to do that, so people are validating ideas first on FPGAs.
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- reportingsjr 11y agoA microcontroller based on RISC-V was announced recently called the pulpino [1]. They actually produced some silicon recently, but unfortunately they don't have plans to sell any. It would be so much fun to play around with a fully open micro! [1]http://www.pulp-platform.org/ http://www.pulp-platform.org/
- razer6 11y agoYou can start playing on FPGAs. There are prebuilt Xilinx images for PULPino :)
- Animats 11y agoThis is a paper CPU, right? You can't actually buy an IC. Even though there's a Linux port for it and four annual conferences so far. There seem to be too many CPU options. Multiply and divide as an option belongs down at the 50 cent 8-bit CPU that runs a microwave oven, not on something that runs Linux. Optional floating point is maybe OK, although you should be able to trap if it's not implemented and do it in software. You don't want to have zillions of builds with different option combinations. That drove MIPS users nuts. The protection levels are still undefined; "User" mode is designed, but what happens at Supervisor, Hypervisor, and Machine mode? If this were well-defined and cheap tablets were coming out of Shentzen using it, it would be important.
- _chris_ 11y ago> This is a paper CPU, right? What? No, it's an Instruction Set Architecture. It's the language the CPU speaks. > Multiply and divide as an option belongs down at the 50 cent 8-bit CPU that runs a microwave oven, not on something that runs Linux Irrelevant, nobody has to know your CPU doesn't implement multiply/divide, not even the OS!; you trap to machine mode and life goes on. And not every RISC-V core needs to run Linux. > but what happens at Supervisor, Hypervisor, and Machine mode? You read the manual that exists, implement the privileged spec, and it'll run Linux. Just because it's not frozen doesn't mean that many RISC-V cores can't already boot a number of different operating systems. > If this were well-defined and cheap tablets were coming out of Shentzen using it, it would be important. There are already shipping products with RISC-V cpus (like in cameras). Just because you're not the customer doesn't mean this work isn't very important to other people.
- zik 11y agoThere are multiple open source implementations of it available, written in hardware description languages. You can program those on to an FPGA or even make an ASIC if your budget extends to that. The http://www.lowrisc.org/ http://www.lowrisc.org/ lowRisc guys are working on an ASIC if you need a real chip.
- IshKebab 11y agoI agree about too many CPU options. It's a pain with ARM Cortex, but I'm not sure of a way around it. I think this ISA is designed to go down to the Cortex M0 level (which also lacks hardware divide). Being about to trap out of it and switch to software seems like a good system - do any other processors work like that?
- bogomipz 11y agoHow do these compare to the Power8 chips? I know Power8 is targeting supercomputers, government research and some large banks.
- _chris_ 11y agoThere are a million things that influence performance to a greater degree than the ISA. However, there's no reason to believe you can't make a perfectly good high-performance RISC-V processor. In my own benchmarking of ARM, x86, and RISC-V CPUs, I've found bigger differences between different GCC compiler versions than between ISAs themselves.
- PeCaN 11y agoIt doesn't. How does Apple's A9X compare to a Xeon E7? RISC-V is excellent for hobbyist boards, mobile CPUs, high-efficiency low-performance servers, as a base for DSPs, high-efficiency network equipment, etc. Everything from the DSP in your phone to a Rasperry Pi to a Macbook Air. POWER8 is excellent for high-performance computing, supercomputers, and workstations (Talos[1] when?! :( ). Things like CAPI, Nvlink, etc—stuff that's well outside the scope of RISC-V (though I suppose you could make an ISA targeting HPC based on the RISC-V base integer ISA, but it would only tangentially resemble RISC-V by the time you're done). Personally I'm looking forward to using both of them in the future! 1. https://raptorengineeringinc.com/TALOS/prerelease.php https://raptorengineeringinc.com/TALOS/prerelease.php
- bogomipz 11y agoThe Talos stuff looks interesting but $3,700 is a bit of sticker shock. Hopefully demand and economies of scale will drive down those price points.
- nickpsecurity 11y agoPOWER has been overpriced for too long. From my past looks at catalogs, paying $3,700 today would be a steal to get a high-performance, POWER workstation. Not necessarily competitive price/performance with Intel but certainly with older RISC workstations.
- YesThatTom2 11y agoWhere's the inscrutable register names? Where's the complex instruction decode? Where's the legacy modes that date back to 1960?? THIS WILL NOT STAND! WHO WOULD WANT TO USE THIS???
- nickpsecurity 11y agoSeriously, they need to read Worse is Better before they get into a bad situation trying to build The Right Thing. Maybe start cranking out x86 clones to sell off to Intel later on. That's a technology that's paid off several times. Even Intel couldn't market a superior processor [1] [2]. Sets the bar high for the little guys. ;) Note: The manual in Wikipedia link describes full ISA and features. It was actually a bad-ass CPU design. I'd really like to know what process node the remaining one's run at. Couldn't find it, though. [1] https://en.wikipedia.org/wiki/Intel_i960 https://en.wikipedia.org/wiki/Intel_i960 [2] http://www.intel.com/design/i960/ http://www.intel.com/design/i960/
- bogomipz 11y agoThis is all interesting. I have question about the "Free and Open" part. Does this mean I could go and manufacture a an FPGA that implements this ISA and sell a product that uses it?
- _chris_ 11y agoYes. You can do whatever you want, even extending or changing the ISA as you want (though if you break I-subset compatibility, the only thing you can't do is still call it a RISC-V processor).