vardump

27 ms·

1. 481.▲
   by vardump 2y ago

   Yes, but it's not going to be speedy, as it is just a dumb framebuffer and the maximum resolution is 1920x1080. The most modern feature is probably double buffering. :-)
2. 482.▲
   by vardump 2y ago

   RP2040/2350 are IO monsters. You could for example make a logic analyzer that transfers logic data through ethernet. This "very limited" microcontroller has two cores. Both of them can execute about 25 instructions per byte f
3. 483.▲
   by vardump 2y ago

   Maybe a lot of CRC errors or something. Just a guess.
4. 484.▲
   by vardump 2y ago

   Impressive. At first I thought it was the new Pico 2 (RP2350), but no, it’s the old Pi Pico with RP2040.
5. 485.▲
   by vardump 2y ago

   I don't think anyone is feeling bad for Boeing's executives. But can feel sorry for the rest of the organization and the subcontractors. Blameless parties are going to suffer a lot of collateral damage.
6. 486.▲
   by vardump 2y ago

   For example use mmap and just assume 4 kB pages.
7. 487.▲
   by vardump 2y ago

   If you have a suitable workload, you do get nearly 100% improvement. There are 2x FPU resources now. Obviously less with generic code. Amdahl’s law and all.
8. 488.▲
   by vardump 2y ago

   Doubling floating point performance is disappointing?
9. 489.▲
   by vardump 2y ago

   For performance sensitive code memory bandwidth is very often the limiting factor, thus compressing values tends to make a lot of sense. The number of CPU cores is increasing much faster than memory bandwidth. So not necessarily completely
10. 490.▲
    by vardump 2y ago

    On the PC side, most developers stopped predominantly using fixed point for high performance code somewhere in the Pentium 1-3 era. For 486 class systems it was still pretty useful. Other than on retro systems, fixed point is still useful i
11. 491.▲
    by vardump 2y ago

    For example Crucial T705 [0] can do 14.1 GB/s sequential reads. That's 113 Gbps. Requires PCIe5, though. A lot of "old" NVMe disks can also do over 50 Gbps. Samsung 980/990, WD SN850X come to mind right away. You co
12. 492.▲
    by vardump 2y ago

    > while the rp2040 was limited to 1/10th of the system Isn't RP2040 capable of outputting at system clock rate?
13. 493.▲
    by vardump 2y ago

    So roughly 19 Mbps, up and down? Although I guess ping is not an optimal bandwidth test.
14. 494.▲
    by vardump 2y ago

    Some "SIMD"-like instructions are included (saturation, add, subtract, multiply), but they all use the scalar register file. So somewhere in between.
15. 495.▲
    by vardump 2y ago

    As if that depends on the engineers! When you make 1M thingies, $5 savings each means $5M CEO comp.
16. 496.▲
    by vardump 2y ago

    You'd hopefully have several launch vehicles ready to return to Earth on Mars at different geographical locations.
17. 497.▲
    by vardump 2y ago

    > I've asked him to write this up to go in a future rev of the datasheet. Thanks!
18. 498.▲
    by vardump 2y ago

    Yes and no. Plenty of such applications that use a µC + an FPGA. FPGA interfaces with some DDR memory and CMOS/CCD/whatever. Up to you what you call it.
19. 499.▲
    by vardump 2y ago

    > 6 cycles for dadd/dsub I guess it depends whether you store to X (or Y), normalize & round (NRDD; is it really necessary after each addition?) and load X back every time. Both X and Y have 64 bits of mantissa, 14 bits of expon
20. 500.▲
    by vardump 2y ago

    Thanks for a great product! A (small?) ask. Can we have instruction timings please? Like how many cycles SMLAL (signed multiply long, with accumulate) takes? Will there be an official development board with all 48 GPIOs exposed?
21. 501.▲
    by vardump 2y ago

    It's a pretty generic µC, especially well suited for projects that require high-speed (GP)I/O. It can replace an FPGA in some cases. DSP extensions and FPU support are also decent, so good for robotics, (limited) AI, audio, etc. A
22. 502.▲
    by vardump 2y ago

    Any concrete examples? PIO is surprisingly flexible, even more so in RP2350.
23. 503.▲
    by vardump 2y ago

    1920x1080 30 Hz DVI would require running RP2350 at least at 311 MHz ((1920 * 1080 * 30Hz * 10) / 2). Probably a bit more to account for minimal horizontal and vertical blanking etc. Multiplier 10 comes from 8b10b encoding. To fit in 5
24. 504.▲
    by vardump 2y ago

    M33 does not have SIMD. No Helium or anything else. DSP extensions are included, but those are all scalar.
25. 505.▲
    by vardump 2y ago

    If the cores share resources like ALU, routing, multiplier, etc. you can't run two cores that share same circuitry at same time. Edit: Correction: Eben Upton said the cores share no logic. https://news.ycombinator.com/i
26. 506.▲
    by vardump 2y ago

    Just pick whatever fits best in your application. No µC is going to solve everything for everyone. RP2350 is about the best I can think of for interfacing with legacy protocols. Well, short of using FPGAs anyways.
27. 507.▲
    by vardump 2y ago

    There are plenty of embedded applications that require megabytes or even gigabytes. For example medical imaging. As well as plenty that require 16 bytes of RAM and a few hundred bytes of program memory. And everything in between.
28. 508.▲
    by vardump 2y ago

    RP2040 had Doom ported to it. https://kilograham.github.io/rp2040-doom/ RP2350 looks very much like it could potentially run Quake . Heck, some of the changes almost feel like they're designed for this purpose. F
29. 509.▲
    by vardump 2y ago

    Assuming Intel is changing direction right now, unfortunately they will face 2-3 years of latency to implement that.
30. 510.▲
    by vardump 2y ago

    I've been wondering if something similar happened to Maxtor and Seagate.