> 6 cycles for dadd/dsub I guess it depends whether you store to X (or Y), normalize & round (NRDD; is it really necessary after each addition?) and load X bac

> 6 cycles for dadd/dsub I guess it depends whether you store to X (or Y), normalize & round (NRDD; is it really necessary after each addition?) and load X back every time. Both X and Y have 64 bits of mantissa, 14 bits of exponent and 4 bits of flags, including sign. Some headroom compared to IEEE 754 fp64 53 mantissa and 11 bits of exponent, so I'd assume normalization might not be necessary after every step. The addition (X = X + Y) itself presumably takes 2 cycles; running coprocessor instructions ADD0 and ADD1. 1 cycle more if normalization is always necessary. And for the simplest real world case, 1 cycle more for loading Y. Regardless, there might be some room for hand optimizing tight fp64 loops. Edit: This is based on my current understanding of the available documentation. I might very well be wrong.