sylware

29 ms·

601.
by sylware 1y ago
I have been using only basic RISC-V core machine instructions: the interpreter is beyond stupid, I did write it directly in x86_64 assembly.
602.
by sylware 1y ago
I am coding my own wayland compositor, in rv64 assembly... running on x86_64 with a small interpreter. I am currently only using the core ISA (no compressed instructions, not even the pseudo instructions), and I use a C preprocessor to avoi
603.
by sylware 1y ago
dav1d is AV1 decoding with C code just for posture: nearly everything is assembly using vector machine instructions from arm64 to x86_64 avxNNN, and of course risc-v. I don't even mention ffmpeg. RVAXX looks like more a grab bag to mat
604.
by sylware 1y ago
I do write RISC-V, x86_64 assembly, and I had to code a bit of ARM64 assembly (because of an old RPI). Well, could not really make the difference between RISC_V and ARM64.
605.
by sylware 1y ago
Please, be my guest.
606.
by sylware 1y ago
At least, I did not choose the side of an ISA with global super strong IP locks like some... There are much more toxic fan boys than some other fan boys...
607.
by sylware 1y ago
???? Do I really need to add "on the long run"? Because this is super obvious. That stuff does not happen over night :) You can feel already the pressure of arm fan boys attacking aggressively RISC-V stuff. This is a good sign. Do
608.
by sylware 1y ago
It seems microsoft GPT oX still using its bullet points output, still completely missing the point without explicit technical context (here the technical context is heavy and implicit).
609.
by sylware 1y ago
If what I read was right, the flags decision was made because RISC-V designers knew it is an awful pain for large out-of-order implementations. It is basically feedback from experience. I guess there is much more advantages to only that. It
610.
by sylware 1y ago
Well, stop missing the point from light years away like LLMs each time there is a strong non-explicit technical context.
611.
by sylware 1y ago
Ofc arm people will go after risc-v: it is a death sentence for them... Come on... But a real-life ISA doing a good enough job, without any global strong IP locks like x86-64 or arm... yummy.
612.
by sylware 1y ago
RISC-V is the better sweet-spot, and has no strong IP locks like arm or x86_64. Not to mention the silicon of nowdays changes everything: you avoid silicon design complexity as much as possible since it will be more than performant enough f
613.
by sylware 1y ago
There is a rational for (compare + branch) in one instruction if I recall properly: no status flags register, which makes out-of-order CPU design much easier and more. Again, the bulk of the programs out there don't need those extensio
614.
by sylware 1y ago
You are still ignoring what I say. Stop using AI, thx.
615.
by sylware 1y ago
This document is not splitting the 'document' from the 'presentation'... and forgetting about noscript. Maybe "HTML" should be replaced with 'Web App'?
616.
by sylware 1y ago
Please, Mister Bezos: fix amazon shop to work again with noscript/basic (x)html browsers (like lynx). (oh, and keep on eye on all those 'internet scanners', 'script kiddies' using AWS for scans/attacks, honey p
617.
by sylware 1y ago
Come on, what was to be understood is to 'stick to the core ISA' as much as possible. I had to clarify the obvious: if a program does not need more than a conservative usage of the ISA to run at reasonable speed, no hardcore chang
618.
by sylware 1y ago
It is sort of obvious and 101: with a heavy technical context "not spoken explicitely", LLMs fail hard and they end up trolling. Usually they completely miss the point, that in a row, like here. Let's start over for microsoft
619.
by sylware 1y ago
Allright, now this is ridiculous. Stop using AIs and/or trolling, thx.
620.
by sylware 1y ago
What??? Re-read my post, please. The problem is those machine instructions not bringing much more than the core ISA which do not require an ISA extension.
621.
by sylware 1y ago
"sweet spot"
622.
by sylware 1y ago
What?? Ofc, if your program uses floating point calculations you will want to use the hardware machine instructions for that. Here, we were talking about about all those machine instructions which do not bring much more on top of the core I
623.
by sylware 1y ago
Compressed instruction only matter for niche (and even in such niche, nowadays, I guess it is very probably very questionable), here you would not use compressed instructions, just the right instruction pattern for fusion, like div/rem
624.
by sylware 1y ago
RISC-V instructions are pretty good, without any IP lock like ARM or x86_64.
625.
by sylware 1y ago
Can the rust toolchain statically link libgcc on elf/linux now? Because this bug is annoying in order to distribute, for instance, game binaries.
626.
by sylware 1y ago
Linus T. is still holding the line... but for how long... because there are already a lot of cracks: look at the compiler requirements to built it, for instance it is missing the assembly code to build it without inline assembly, and some c
627.
by sylware 1y ago
And a few months ago, they did, literaly, block noscript/basic (x)html browsers for their dominant search engine (right before that they were white-listing a few of those browsers). Gogol has been on the super evil guys side for a whil
628.
by sylware 1y ago
I feel ok for closed source applications being coded using the computer languages of their choice. But regarding rust, on elf/linux, please fix the toolchain in order to statically link libgcc (at best this is a private dependency of t
629.
by sylware 1y ago
This is implemented with instruction fusion. Just need to document properly and publish properly what will end up "standard instruction fusion patterns" (like the div/rem one). Adding more instructions is kind of non producti
630.
by sylware 1y ago
Very often, I have a look at steam "released" and "upcoming" (only the native elf/linux titles though). Basically, it is only trash, and sometimes you do stumble across what looks like a real game. And among those l

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