4 ms·

Ofc arm people will go after risc-v: it is a death sentence for them... Come on... But a real-life ISA doing a good enough job, without any global strong IP l

Ofc arm people will go after risc-v: it is a death sentence for them... Come on... But a real-life ISA doing a good enough job, without any global strong IP locks like x86-64 or arm... yummy.

thesz 1y ago
> Highly unconstrained extensibility. While this is a goal of RISC-V, it is also a recipe for a fragmented, incompatible ecosystem and will have to be managed with extreme care. This is taken straight from the ISA specification. For example, Intel can brand their own chips as RISC-V-ZIntelx8664, if they want to, because RISC-V-Zxxx implementation can be as incompatible with any other RISC-V implementations (and even specification) as one wants.
- tux3 1y ago
  >RISC-V-Zxxx implementation can be as incompatible with any other RISC-V implementations (and even specification) as one wants. It can't. Extensions have a lot of freedom, but still have to follow the core spec. You can't just submit amd64 as a riscv extension for a myriad of reasons, it clearly conflicts with the base ISA. This is also why there is a trademark. If you or Intel wanted to deliberately create nonsense to be disruptive, you are allowed to create it, but then you can't call it RISC-V without receiving some fan-mail from lawyers.
  - wren6991 1y ago
    ...although you could certainly implement a Jazelle-style "branch to x86" instruction if you really wanted. It's fine as long as you come up in RVI mode. Unfortunately you would not be able to repurpose the LSB of jalr targets as an "x86 bit" à la Thumb because the standard requires you to ignore that bit, though of course you could enable that behaviour with a custom CSR.
  - camel-cdr 1y ago
    What you could do is add a custom vendor extension, maybe XIntel64, which adds a CSR that can toggle between RISC-V and x86 mode.
- hajile 1y ago
  Honestly, I think the RISC-V guys would LOVE a dual x86/RISC-V hybrid processor as it would make the transition much more smooth.
compiler-guy 1y ago
A quick Google search for the number of processors shipped in 2024 shows nVidia shipping one-billion riscv _cores_ last year being pretty big news. Assuming they were one fourth of the market, and that there was just one core per chip (certainly not true) that’s four billion cores. Meanwhile arm licensees shipped twenty-nine billion chips. Most with four cores, and some with many more. Riscv is on the way up, but any death sentence for arm is decades away.
- sylware 1y ago
  ???? Do I really need to add "on the long run"? Because this is super obvious. That stuff does not happen over night :) You can feel already the pressure of arm fan boys attacking aggressively RISC-V stuff. This is a good sign. Don't forget: RISC-V has no strong IP ISA locks like arm and x86_64...
  - compiler-guy 1y ago
    In the long run we are all dead. So a “death sentence” far enough out is meaningless. Riscv killing arm is pretty distant. They will all be replaced sooner or later. I have no particular affinity for arm or riscv. Playing fan-boi for any technology is silly.
    - sylware 1y ago
      At least, I did not choose the side of an ISA with global super strong IP locks like some... There are much more toxic fan boys than some other fan boys...
- hajile 1y ago
  Qualcomm is rumored to be paying 2-2.5% per chip instead of the 5-5.5% ARM sued them for (some sources claim it was 6-10%). No matter how you slice up their handset and mobile divisions profits, the current cost is billions just to license an ISA. Qualcomm could likely pay for most of their chip design costs with the amount of money they’re giving ARM. When contract renewal comes up, Qualcomm will be even more incentivized to move to RISC-V. Apple has apparently been moving on chip soft cores to RISC-V. At some point (probably around renewal time), they’re likely to want to save money by switching to RISC-V too. There are even rumors of ARM working on RISC-V cores (I’d guess smaller cores to compete with SiFive). There’s an economic incentive to change and the only blocker is ARM inertia, but making ARM emulate quickly on RISC-V is almost certainly easier than making x86 and all its weirdness/edge cases run on ARM. Once the software is in place (getting close) and a competitive RISC-V phone chip exists, I suspect the conversion will be very fast.

Ofc arm people will go after risc-v: it is a death sentence for them... Come on... But a real-life ISA doing a good enough job, without any global strong IP locks like x86-64 or arm... yummy.

thesz 1y ago

> Highly unconstrained extensibility. While this is a goal of RISC-V, it is also a recipe for a fragmented, incompatible ecosystem and will have to be managed with extreme care. This is taken straight from the ISA specification. For example, Intel can brand their own chips as RISC-V-ZIntelx8664, if they want to, because RISC-V-Zxxx implementation can be as incompatible with any other RISC-V implementations (and even specification) as one wants.

tux3 1y ago
>RISC-V-Zxxx implementation can be as incompatible with any other RISC-V implementations (and even specification) as one wants. It can't. Extensions have a lot of freedom, but still have to follow the core spec. You can't just submit amd64 as a riscv extension for a myriad of reasons, it clearly conflicts with the base ISA. This is also why there is a trademark. If you or Intel wanted to deliberately create nonsense to be disruptive, you are allowed to create it, but then you can't call it RISC-V without receiving some fan-mail from lawyers.
- wren6991 1y ago
  ...although you could certainly implement a Jazelle-style "branch to x86" instruction if you really wanted. It's fine as long as you come up in RVI mode. Unfortunately you would not be able to repurpose the LSB of jalr targets as an "x86 bit" à la Thumb because the standard requires you to ignore that bit, though of course you could enable that behaviour with a custom CSR.
- camel-cdr 1y ago
  What you could do is add a custom vendor extension, maybe XIntel64, which adds a CSR that can toggle between RISC-V and x86 mode.
hajile 1y ago
Honestly, I think the RISC-V guys would LOVE a dual x86/RISC-V hybrid processor as it would make the transition much more smooth.

compiler-guy 1y ago

A quick Google search for the number of processors shipped in 2024 shows nVidia shipping one-billion riscv _cores_ last year being pretty big news. Assuming they were one fourth of the market, and that there was just one core per chip (certainly not true) that’s four billion cores. Meanwhile arm licensees shipped twenty-nine billion chips. Most with four cores, and some with many more. Riscv is on the way up, but any death sentence for arm is decades away.

sylware 1y ago
???? Do I really need to add "on the long run"? Because this is super obvious. That stuff does not happen over night :) You can feel already the pressure of arm fan boys attacking aggressively RISC-V stuff. This is a good sign. Don't forget: RISC-V has no strong IP ISA locks like arm and x86_64...
- compiler-guy 1y ago
  In the long run we are all dead. So a “death sentence” far enough out is meaningless. Riscv killing arm is pretty distant. They will all be replaced sooner or later. I have no particular affinity for arm or riscv. Playing fan-boi for any technology is silly.
  - sylware 1y ago
    At least, I did not choose the side of an ISA with global super strong IP locks like some... There are much more toxic fan boys than some other fan boys...
hajile 1y ago
Qualcomm is rumored to be paying 2-2.5% per chip instead of the 5-5.5% ARM sued them for (some sources claim it was 6-10%). No matter how you slice up their handset and mobile divisions profits, the current cost is billions just to license an ISA. Qualcomm could likely pay for most of their chip design costs with the amount of money they’re giving ARM. When contract renewal comes up, Qualcomm will be even more incentivized to move to RISC-V. Apple has apparently been moving on chip soft cores to RISC-V. At some point (probably around renewal time), they’re likely to want to save money by switching to RISC-V too. There are even rumors of ARM working on RISC-V cores (I’d guess smaller cores to compete with SiFive). There’s an economic incentive to change and the only blocker is ARM inertia, but making ARM emulate quickly on RISC-V is almost certainly easier than making x86 and all its weirdness/edge cases run on ARM. Once the software is in place (getting close) and a competitive RISC-V phone chip exists, I suspect the conversion will be very fast.