pm215

42 ms·

451.
by pm215 5y ago
No, this works fine for symmetric configs. The OS can treat all the CPUs the same once they've booted, you just need to pick one of them arbitrarily to run the initial bootup code, which is conventionally the one with ID 0. Calling tha
452.
by pm215 5y ago
The code that runs at startup makes sure they don't all write to the same location :-) A common simple approach goes: * read the CPU main ID register * if core 0, branch to primary-core bootup code * otherwise, go into a loop
453.
by pm215 5y ago
On Arm a couple of only-on-hardware pitfalls are (a) cache maintenance -- QEMU doesn't model caches so won't notice if you forget to clean the dcache and flush the icache before executing code you just wrote or modified and (b) sy
454.
by pm215 5y ago
Not official, and it only covers East Anglia, but I really like this site http://www.suffolkchurches.co.uk/churchlists.htm (and its sister sites covering Norfolk, Cambridgeshire, etc). It's just one person, who's
455.
by pm215 5y ago
That's the Fred Brooks "chief programmer" model that the post mentions in the first paragraph. Brooks describes it in one chapter of _The Mythical Man Month_, which is one of those rare cases of a book in the tech field that
456.
by pm215 5y ago
Personally I think that is pessimal, because if I am the person investigating in 5 years time I want to see the change split up into multiple logical commits. So lots-of-commits-plus-squash-and-merge requires the developer to do the work of
457.
by pm215 5y ago
You're not kidding about the limited coverage -- their website shows nothing except some trail maps over the whole of southern England with the exception of Dartmoor. And southern England is where I am so it's where I walk mostly.
458.
by pm215 5y ago
If you want to walk, as opposed to just get somewhere in a car, I have yet to find anything better than an OS map. Google Maps is hopeless for footpaths; OpenStreetMaps is a bit better but it depends a lot on whether somebody enthusiastic h
459.
by pm215 5y ago
Unfortunately as UI a 7 character option is almost always going to win over an 18 character option. I know about --force-with-lease, I know that it would provide an extra safety guard, and I always use --force anyway because it's the s
460.
by pm215 5y ago
It was our family's first computer in the UK -- pretty sure my Dad picked it up very cheap when the local department store were getting rid of the last of their stock after TI killed the machine. The lack of commercial games for it com
461.
by pm215 5y ago
The Arm ARM says FNMADD is "Floating-point Negated fused Multiply-Add", so the position of the hyphens points strongly to "n(madd)" rather than "(nm)add".
462.
by pm215 5y ago
In the spec, the pseudocode defines them as FMADD: addend + ( op1 * op2) FMSUB: addend + (-op1 * op2) FNMADD: -addend + (-op1 * op2) FNMSUB: -addend + ( op1 * op2) which is to say that in all three cases the result is t
463.
by pm215 5y ago
QEMU doesn't hook execve anyway, at least not upstream -- when a QEMU emulated process invokes another we rely on the binfmt-misc magic to cause the kernel to run QEMU on the child. We don't special case "the binary being exe
464.
by pm215 5y ago
This is the same trick used by the old 'scratchbox' development environment that Nokia used for the maemo SDK. If the stuff you compile in it includes classic "configure and make" C/C++ projects then you'll pro
465.
by pm215 5y ago
The article's answer to this question is "the eventuality of endemic COVID-19 does not mean we should drop all precautions. The more we can flatten the curve now, the less hospitals will become overwhelmed". There are current
466.
by pm215 5y ago
It's the required semantics of the IEEE floating point spec's absolute-value operation. This does mean that abs() doesn't behave like eg addition in that it won't set fp exception flags for signaling NaNs, or canonicaliz
467.
by pm215 5y ago
If you check out the end of the thread you can see that they stayed overnight in a hotel in Morecambe and took the train back the next morning. There wouldn't be a train to catch at gone midnight when they arrived in Morecambe (the las
468.
by pm215 5y ago
Wasn't Top of The Pops all film of the bands in a studio live/miming-over-a-recording, though? I don't see how that would provide a head-start for producing music videos...
469.
by pm215 5y ago
I've done the "reference the spec section" thing before -- the difficulty is that often section numbers or similar things get stale when a newer revision of the spec document is published; so it can work for a slow-moving thi
470.
by pm215 5y ago
If your CPU has vector/SIMD instructions then you might want fp16 format support for data processing so that you can operate on (say) a 128-bit vector of 8 fp16 values at once, rather than having to work with 4 fp32 values at a time. B
471.
by pm215 5y ago
I think it's not so much that the IEEE f32/f64 choice was necessarily perfect so much as that it was "good enough", and so it's not worth the hardware costs of handling multiple formats or the headaches of picking a
472.
by pm215 5y ago
Alternative-halfprec format only applies for conversions (ie to/from single and double prec); data-processing operations on fp16 ignore the AHP bit and always assume IEEE format. If you convert a NaN from single/double into AHP yo
473.
by pm215 5y ago
For what it's worth, the Arm "alternative half-precision" format is not very different from IEEE binary16. The difference is that instead of using the maximum exponent value (0x1f) to represent infinities and NaNs, the AHP fo
474.
by pm215 5y ago
I'm sympathetic to your overall point, but I'm impressed that you've had zero boiler failures in 30 years. I'm pretty sure that's better than the average. (Mine is about 10 years old and has needed one fairly minor
475.
by pm215 5y ago
I get the impression that this kind of thing depends rather on what specific locked-down settings choices the Exchange admins have made. I use work's Office-365 mail setup (which is I assume basically "exchange in the cloud")
476.
by pm215 5y ago
Random nitpick from the middle of a good writeup of tracking down a hardware bug, but 'SMC' in this context doesn't stand for 'Secure Memory Controller'. It's the Arm instruction that lets normal-world (kernel)
477.
by pm215 5y ago
I think if you asked these universities they would say that they are taking the very long term view. (For instance the one I went to has been around for 800 years already.) If you are thinking on a timescale of centuries then you want to t
478.
by pm215 5y ago
It's Qn when you're dealing with the register as a single 128-bit quantity (currently only the SHA256 and SHA512 insns need to do this, I think, judging from a quick search through the architecture reference manual), and Vn when y
479.
by pm215 5y ago
For 64-bit Arm FPU registers, the mapping is extremely simple: Q0 is the 128-bit vector register; D0 is the bottom 64 bits of it; S0 is the bottom 32 bits; H0 is the bottom 16 bits; B0 is the bottom 8 bits. Similarly Q1/D1/S1&#x2F
480.
by pm215 5y ago
I use it all day every day, and I really like it for the workflows I have, which are basically contributing to open source projects that use the "send patches by email for review, features should be sent as patch series with each commi

More ›