njv4567

3 ms·

1. 1.▲
   by njv4567 8y ago

   Hey good question...trust me i wish they were eBPF ASICs :p. So we have a general purpose Compute engine, it is a processor in the same way ARMs/X86’s etc are BUT it has an instruction set which is optimized for networking, and as well
2. 2.▲
   by njv4567 8y ago

   Yeah-i showed a couple of things with regards to latency in the report...i also posted another graph on my very empty twitter (@viljoen_nic). We get massive improvements, especially in the tail latency cases, due to not passing across PCIe.
3. 3.▲
   by njv4567 8y ago

   So I believe at the moment we allocate about 1GB of on card DRAM backed storage for lookups, but the chip supports way more DRAM (8GB) and there are other larger chips that can support way more even (up to 24GB). But we have focused on this
4. 4.▲
   by njv4567 8y ago

   Hey Man! Thanks for the comment. Yeah, maybe i assumed that not this many people would who werent already familiar would see this :) The NFP is our many core processor with 72 cores (50 used for BPF) each of those cores has 8 threads which