Hey good question...trust me i wish they were eBPF ASICs :p. So we have a general purpose Compute engine, it is a processor in the same way ARMs/X86’s etc are B

Hey good question...trust me i wish they were eBPF ASICs :p. So we have a general purpose Compute engine, it is a processor in the same way ARMs/X86’s etc are BUT it has an instruction set which is optimized for networking, and as well as a ton of threads also has a giant amount of registers. These teo properties mean that mapping bpf bytecode (effectively a networking ISA) to our assembler (also a networking ISA) is relatively simple...if you are interested check out the code from our upstream JIT in the Linux kernel. That will show you how the whole thing fits together :)