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nelsonje
searching PlanetScale…
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by
nelsonje
8y ago
This is the canonical Cilk paper: http://supertech.csail.mit.edu/papers/cilk5.pdf
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by
nelsonje
12y ago
I asked some of the authors about this---it sounded like the primary reason was that, in the FPGAs they were considering, the Altera PCIe endpoint was much better behaved than the Xilinx one (due to excessive link training time, IIRC).