I asked some of the authors about this---it sounded like the primary reason was that, in the FPGAs they were considering, the Altera PCIe endpoint was much bett

I asked some of the authors about this---it sounded like the primary reason was that, in the FPGAs they were considering, the Altera PCIe endpoint was much better behaved than the Xilinx one (due to excessive link training time, IIRC).