marcux95

6 ms·

1. 1.▲
   Tiny-Vedas: a generic accelerator interface for RISC-V, from PyTorch op to GDS(github.com)

   2 points by marcux95 2mo ago|0 comments
2. 2.▲
   My Mental Sanity Script on OpenWRT(gist.github.com)

   1 points by marcux95 1y ago|1 comments
3. 3.▲
   by marcux95 1y ago

   When news is just too much
4. 4.▲
   ECC SystemVerilog Generator(github.com)

   7 points by marcux95 1y ago|0 comments
5. 5.▲
   How to Compile a Large Language Model (LLM) to RISC-V(siliscale.com)

   4 points by marcux95 1y ago|0 comments
6. 6.▲
   RISC-V Processor Design – Lec 6 – EXU and Co-Simulation

   5 points by marcux95 2y ago|1 comments
7. 7.▲
   RISC-V CPU Design – Lec 5 – Design Top Level and Testbench, Instruction Decode(youtube.com)

   3 points by marcux95 2y ago|0 comments
8. 8.▲
   Lecture 4 of how to design a RISC-V Processor available [video](youtube.com)

   3 points by marcux95 2y ago|0 comments
9. 9.▲
   New free course on RISC-V processor design on YouTube(youtube.com)

   5 points by marcux95 2y ago|1 comments
10. 10.▲
    by marcux95 2y ago

    Hey guys, I've been working for 10+ years in the RISC-V space (mainly AI and Network Packet processing accelerators) and teaching RISC-V computer architecture classes for 6+ years at both grad and undergrad levels. I got my PhD last ye