kassane

4 ms·

1. 1.▲
   by kassane 3y ago

   So don't wait. Tarballs already available for testing[1] and an example using esp-idf.[2] [1]: https://github.com/kassane/zig-espressif-bootstrap/releases [2]: https://github.com/kassane/
2. 2.▲
   by kassane 3y ago

   Unfortunately, the upstream zig toolchain (LLVM codegen) does not support the Xtensa architecture (opaque CPU features), but it is possible to use riscv32 for esp32 from the C2/C3/C6, H2 and the new P4 release. I'm currently
3. 3.▲
   by kassane 4y ago

   There are some projects trying to bring this experience. https://github.com/ibokuri/concepts https://github.com/mov-rax/zig-validate https://github.com/yrashk/zig-ctc