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Unfortunately, the upstream zig toolchain (LLVM codegen) does not support the Xtensa architecture (opaque CPU features), but it is possible to use riscv32 for e
by kassane 3y ago
Unfortunately, the upstream zig toolchain (LLVM codegen) does not support the Xtensa architecture (opaque CPU features), but it is possible to use riscv32 for esp32 from the C2/C3/C6, H2 and the new P4 release.
I'm currently working on a fork of the zig toolchain with espressif-LLVM to support Xtensa.[1]
It is now possible to test with esp-idf instead of microzig for baremetal (Blink) yet.
[1] https://gist.github.com/kassane/7bdb782a1984d0c6581ae7b44e1fc0c2 https://gist.github.com/kassane/7bdb782a1984d0c6581ae7b44e1f...
- 22c 3y agoYeah I remember reading about it's relation to LLVM issues etc. I also think there was another (languishing) fork of the entire zig repo which had some support for Xtensa which I couldn't find at the time, but I found it. https://github.com/ominitay/zig/tree/xtensa https://github.com/ominitay/zig/tree/xtensa Edit: I see you are the same kassane from the GitHub thread. Thank you for your efforts on Xtensa support! Would be great to have it out-of-the-box at some point.
- kassane 3y agoSo don't wait. Tarballs already available for testing[1] and an example using esp-idf.[2] [1]: https://github.com/kassane/zig-espressif-bootstrap/releases https://github.com/kassane/zig-espressif-bootstrap/releases [2]: https://github.com/kassane/zig-esp-idf-sample https://github.com/kassane/zig-esp-idf-sample