iron2disulfide

5 ms·

1.
by iron2disulfide 3y ago
I find your company fascinating, having also worked on chips (and chip dev tooling) for much of my career. > But they want to work on chips, not devtools! I have long had a gut feeling that there's an entire industry of frustrating
2.
by iron2disulfide 3y ago
I started my career off in the chip design world, where 100% line, branch, FSM transition, functional group, and toggle (i.e. individual bits in a bus switching 0 -> 1 _and_ 1 -> 0) was "table stakes". There are a lot of com
3.
by iron2disulfide 4y ago
The functionality of the F-91W is simple enough that I don't think a CPU would even be needed. Probably the digital parts of this chip are just state machines. That being said, the left half of the die shot looks like some kind of giga
4.
by iron2disulfide 4y ago
The "Silicon" part of Silicon Valley is still very much relevant. Intel, AMD, nVidia, etc. all have major presences down there. There's also a multi-billion dollar industry supporting silicon design shops in various ways, and
5.
by iron2disulfide 4y ago
Gate-level simulation (even zero-delay, let's not mention delay-aware or even power-aware) for a modern-sized CPU takes weeks just to run through some basic liveliness checks. See [1] for just a taste of gate-level simulation trickines
6.
by iron2disulfide 4y ago
> Most don't Is this true? I'm pretty sure that most of the regex engines I've used (grep, ripgrep, re2, hyperscan) use Thompson's construction or at least some NFA-based algorithm (not necessarily Thomopson's; G
7.
by iron2disulfide 4y ago
Based purely on the name and a super quick scroll through the github page, it's probably the Lattice ice-series of chips, even more probably the ice40. There are a couple boards with ice40 chips out there that you can use fully OSS too
8.
by iron2disulfide 4y ago
(Digital) chip designer here: this is super cool. What tech node are you targeting? Have you checked out any of the free open-source tools and PDK from Skywater, Google, eFabless and co?
9.
by iron2disulfide 4y ago
The $1k figure quoted by OP is not indicative of the average price of licenses in my experience. There are plenty of tools that are $15k+ in the EDA world, and various engineers in chip design orgs are always battling about who gets to use
10.
by iron2disulfide 4y ago
I almost got kicked out because I "looked like" someone who had vandalized something or other the day before. They pulled me out of class, called me names, made me sit in their little sad office (thus missing more class) and tried
11.
by iron2disulfide 4y ago
There are still SWEs that use the Linux laptops. There are dozens of us!
12.
by iron2disulfide 4y ago
Related to this, are there any open source audio interfaces, something that can replace a Focusrite 2i2?
13.
by iron2disulfide 4y ago
That makes sense. It kind of seems like the new program will be sort of a mish-mash of ChE, systems eng, and ECE (i.e. what it takes to actually run a fab). In fairness, I think overall there are no curricula specifically about how to run a
14.
by iron2disulfide 4y ago
In chronological order: a fabless IP company, FPGA company, FAANG company. I've since taken a hiatus from chip design.
15.
by iron2disulfide 4y ago
Skimmed the article; what's the difference between this program and what's already taught in electrical and computer engineering classes? I studied ECE for my BS and MS and there were already a couple of chip design-related course
16.
by iron2disulfide 4y ago
I've worked with Samsung Semiconductor as a partner/customer and it did seem to me from the outside that there was a culture of not admitting mistakes/failings, and poor communication between different parts of the company (i
17.
by iron2disulfide 6y ago
TIL about JDK's vector API. That's awesome; I mostly work in the C and C++ space and have learned to embrace the gigantic ifdef's for various arch-specific vectorized instructions.
18.
by iron2disulfide 6y ago
Verilog, VHDL, and SystemVerilog are supported by Vivado. A small subset of C++ is supported through Vivado's high level synthesis compiler, which transforms some C++ code into Verilog. RTL stands for register-transfer level, which is
19.
by iron2disulfide 6y ago
Of course "the same HDL" is a reductive statement, since components like high-speed IO, or even clock gates are not easily portable between FPGA vendors or foundries. But the user-land Verilog/VHDL code that describes how you
20.
by iron2disulfide 6y ago
I'd like to know more about the PCIe Gen2. From your comment it sounds like the root port is capable of Gen2x2, or is it 2x Gen2x1 ports? If I wanted to attach a PCIe accelerator card with a standard PCIe connector, is there some kind
21.
by iron2disulfide 6y ago
Haha, I am kind of the opposite: I work on electronics, and am not much of a sys admin. One of the problems I've run into is that I haven't found a single switch solution with enough connections. I could build a multi-level mult
22.
by iron2disulfide 6y ago
This is cool. Any chance this would scale for many machines? I have a ~15 machine lab with no KVM setup right now, and could really use something like this if it works for a large number of devices.
23.
by iron2disulfide 6y ago
There are a lot of companies who create multi-FPGA boards. The market for FPGAs-for-ASIC-prototyping is substantial.