hajile

42 ms·

691.
by hajile 3y ago
That's Samsung 10nm LP vs something something 7nm. Not the best comparison, but one that would still imply some amount of area advantage for stock 7nm nodes. A78 on SD845 used 64kb L1 vs 32kb L1 on P670 (a 32kb variant is available, bu
692.
by hajile 3y ago
Orange Pi also has a bunch of extra features too including some standout ones like * don't need to spend extra $$ for M.1 SSD support * full-size HDMI so no need for $10 dongle * 6 TOPS NPU * better Mali G610 MP4 GPU * 8k60 output * US
693.
by hajile 3y ago
They use a couple dozen Chinook of soft cores. These are supposedly small 64-bit cores, but ARM requires features they likely don't use and ARM requires payment for each of these cores. Switching these to RISC-V could save area and mon
694.
by hajile 3y ago
Neither side is correct IMO. Qualcomm wants 32-bit only instructions, but that leaves out many use cases that require longer instructions. On the flip side, a 48-bit instruction takes FIVE bits just to specify the length which is a massive
695.
by hajile 3y ago
Even Apple has added job postings for RISC-V devs.
696.
by hajile 3y ago
x86 has turned assembly into voodoo while RISC-V is very simple to understand and teach. This is true at the basic level, but is also true for something like vectors vs AVX where one is quite easy to teach while the other is massively compl
697.
by hajile 3y ago
I have to maximize my terminal so I can slice it into a bunch of tmux and vim windows and make a pseudo-tiled window manager.
698.
by hajile 3y ago
Which is easier to decode? [jmp nop nop], [addi xxx] OR [xxx jmp], [nop nop addi] OR [xxx jmp], [unused, addi] All of these tie up your entire decoder, but some tie it up with potentially useful information. That seems superior to me.
699.
by hajile 3y ago
Your assertion has two major issues. First, you context switch a lot to and from the Linux kernel, so decreased cache pressure does matter. Second, if you have proof that loops predominantly consist of 32-bit instructions, prove your case.
700.
by hajile 3y ago
Consider the Linux kernel code getting 50% larger when you move from compressed to uncompressed instructions[0]. That puts RISC-V as among the least efficient ISAs out there and would make it unsuitable for most applications. [0] https:&#x
701.
by hajile 3y ago
More than 30%. For example, in this 2016 paper, the Linux kernel using compression was 67% the size of the non-compressed instructions. Stated in the reverse, removing compressed instructions would increase the kernel size by 50%. https:&#
702.
by hajile 3y ago
Back in 2019, RISC-V was 15-20% smaller than x86 (up to 85% smaller in some cases) and was 20-30% smaller than ARM64 (up to 50% smaller in some cases). https://project-archive.inf.ed.ac.uk/ug4/20191424/ug4_proj.p..
703.
by hajile 3y ago
RISC-V already has those things and the answer seems pretty clear. P670 gets around the same performance as A78 while being 50% smaller (according to SiFive) while having vectors, atomics, floats, etc.
704.
by hajile 3y ago
I have no idea why it came out as EPYC. I fixed it. Thanks!
705.
by hajile 3y ago
ARM's case is that a uarch is necessarily tied to its ISA and that their license isn't transferrable because the contract plainly says so. If Qualcomm can show up and say "here's our uarch running a different ISA",
706.
by hajile 3y ago
If you're fetching 128-bit cache lines, you're already "wasting" cache. Further, decoding 1-3 NOP instructions isn't much different from decoding 1-3 extra instructions except that it adversely affects total code de
707.
by hajile 3y ago
Qualcomm's Znew proposal is basically an attempt to skirt ARM royalties while keeping a design that is very close to ARM64 (basically, throw out 16-bit instructions then add some new modes and complex 32-bit instructions ARM uses to ma
708.
by hajile 3y ago
x86 is known to work and it has 15 possible lengths instead of just 2 (moreover, those lengths aren't known until decode is already started). Despite this, x86 still holds the crown for fastest overall CPU design. RISC-V compressed ins
709.
by hajile 3y ago
The sweet spot for scalar code is about 24 registers, but that leads to weird offset-bits (there's an ISA that does this, but I forget what it's called), so 32 registers is easier to implement and provides a mild improvement in th
710.
by hajile 3y ago
The packet would be external and always fit in a cache line. You'd specify the exact instruction using 16-bit positioning. The fetcher would fetch the enclosing 64-bit group, decode, then jump to the proper location in that group. In t
711.
by hajile 3y ago
Intel seems to have quite a bit of interest in RISC-V. They even have a pipecleaner chip using a SiFive core with all the rest being Intel IP. RISC-V could be their ticket into the phone space. Finally, Intel knows x86 sucks. They've t
712.
by hajile 3y ago
Not necessarily. 000x -- 64-bit instruction that uses 60 bits 001x -- reserved 010x -- reserved 011x -- reserved 100x -- two 32-bit instructions (each 30-bits) 101x -- two 16-bit instructions then one 32-bit instru
713.
by hajile 3y ago
Personally, I like the idea of doubling the instruction length every time -- 16, 32, 64, 128, etc. There's a big use case on the longer instruction end for VLIW/DSP/GPU applications.
714.
by hajile 3y ago
why is this even the headliner complaint? Post-launch embargoes to deceive consumers about actual performance is a MUCH bigger deal.
715.
by hajile 3y ago
Isn't WebGPU far closer to Metal than to Vulkan or D3D12?
716.
by hajile 3y ago
Hopefully, WebGPU will eat all its competition and we can finally have just one standard moving forward.
717.
by hajile 3y ago
Shift is one cycle. Or is one cycle. If your table is using a fast algorithm, it’s going to add a few more cycles and a couple very predictable branches. Meanwhile, divide is insanely slow. If your table is in L1 or L2 cache, it should be
718.
by hajile 3y ago
If I had access to a dictionary with pronunciation symbols and a thesaurus, I could do it regardless of language. The LLM not only has access, but has baked both its model. This problem is EXACTLY the kind of problem computers should be goo
719.
by hajile 3y ago
If China can make fast RISC-V chips to compete, they can make fast ARM chips to compete too. Artificially limiting software is only going to hold back everyone.
720.
by hajile 3y ago
Qualcomm x24 was 33mm2 on TSMC N7. The max transistor density of that process is 100M/mm2 giving an upper threshold of 3.3B transistors, but analog circuits scale notoriously bad and I wouldn’t be at all surprised if the actual transis

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