gchadwick

13 ms·

91.
by gchadwick 3y ago
Another source here: https://twitter.com/duncan_2qq/status/1773752269395099774 Incredibly sad news, a great loss.
92.
by gchadwick 3y ago
The RP2040 is a great MCU for playing with graphics as it can bit bang VGA and DVI/HDMI. There's some info on the DVI here: https://github.com/Wren6991/PicoDVI I wrote a couple of articles on how to do bit ba
93.
by gchadwick 3y ago
Cool! I found the hello blog here illuminating to understand the creators intentions: https://www.furygpu.com/blog/hello As I read it, it's just a fun hobby project for them first and foremost and looks like they&
94.
by gchadwick 3y ago
For anyone interested in CHERI for embedded/IoT and other similar use cases lowRISC (whom I work for) are building a couple of FPGA based evaluation platforms for CHERIoT (The Microsoft created CHERI variant referred to above): https:
95.
by gchadwick 3y ago
Powerful generative capabilities aren't always as useful as you might think. There's two major issues: 1. Verification - You can verify one particular part of the configuration space but verifying the full generic component is som
96.
Veryl – A modern HDL based on SystemVerilog(veryl-lang.org)
1 points by gchadwick 3y ago|0 comments
97.
by gchadwick 3y ago
CHERI provides actual hardware enforced protection. MTE exists to find potential security bugs but no real protection. You've got a 4 bit tag, which an application can forge so if some attacker needed to forge the correct tag they coul
98.
by gchadwick 3y ago
Whilst I'm often quite sceptical of new HDLs (see my other comment on this post) it is nice to see HDL and other silicon content pop up so often on HN. There's a lot of keen people doing interesting things here and it's great
99.
by gchadwick 3y ago
> My experience with most "neo HDLs" is that they are all code generators which make the tedious part easy and don't really end up touching the hard part. That's generally make take too, only I'd say they make so
100.
by gchadwick 3y ago
They have https://youtu.be/8eAgjgbZyPw?si=ZIBEFLOc_13hitGp Though sadly it's remained a prototype. I think the issue they had was you needed to mod the DE10 Nano (remove the pin headers and I think the ethernet jack) t
101.
by gchadwick 3y ago
Whilst it's true FPGA doesn't inherently imply accuracy it does make it simpler to recreate things in a more accurate way, in particular around interactions between CPU,audio and video. It also enables accurate input latency with
102.
by gchadwick 3y ago
I think it's a bit rich to describe this as the 'future of video game preservation'. The MiSTer project https://github.com/MiSTer-devel/Wiki_MiSTer/wiki more rightfully deserves that title. It'
103.
by gchadwick 3y ago
Stable diffusion (along with other text to image models like Dall-E) use a process called 'latent diffusion'. At the core of a latent diffusion model is a de-noising process. It takes a noisy image and predicts what is noise vs wh
104.
by gchadwick 3y ago
Thanks for the info these all certainly sound like promising developments though I still think there's a major hurdles to overcome. > good PPA with popular backend tools Getting good PPA for any given thing you can express in the la
105.
by gchadwick 3y ago
Yeah I should really get around to learning VHDL!
106.
by gchadwick 3y ago
I think the inherent problem is abstraction just doesn't work in the same way as it does in software. Various things keep pulling you down to the circuit level so if you're too far above it you're going to have a hard time as
107.
by gchadwick 3y ago
Yes, I actually built two CPUs in it (one a derivative of the other) for my PhD over a decade ago. That experience helped shape my view on new HDLs. As a specific example Bluespec has this system of rules that define hardware behaviour. Fro
108.
by gchadwick 3y ago
I've said as much before but I find the issue with alternative HDLs Vs SystemVerilog is they concentrate on fixing annoying and frustrating things but don't address the really hard issues in hardware design and can actually make t
109.
by gchadwick 3y ago
Though on the CoreMark benchmark they haven't published the IPC achieved. You get a large swing in results depending upon the compiler used and switches (For RV32 at least I've found GCC out-performs LLVM comfortably). They do hav
110.
by gchadwick 3y ago
It's a cool project but I do wish these open source processor initiatives targetted more realistic design points. In particular there's often a desire to push out of order design into the micro-architecture where the resulting per
111.
by gchadwick 3y ago
Have you considered running on a cloud machine instead? You can rent machines on https://vast.ai/ for under $1 an hour that should work for small/medium models (I've mostly been playing with stable diffusion so I
112.
by gchadwick 3y ago
They might also know a bunch of techniques to give high performance that only work if you've got nice 32-bit only aligned instructions!
113.
by gchadwick 3y ago
> variable length instructions == CISC is not quite a correct equivalence. Yeah I'd tend to agree, in particular x86 variable length encoding is a lot more complex than the RISC-V encoding! What I'm really getting at is CISC an
114.
by gchadwick 3y ago
As the other reply states that is effectively the Qualcomm proposal though note the 16-bit instructions likely gobble up a large amount of your 32-bit instruction space. You have to have something to identify an instruction as 16-bit which
115.
by gchadwick 3y ago
Yes exactly, the 'existence proof of a competitive architecture using exclusively 32-bit instructions' has often been reference. Qualcomm's proposal is all instructions are aligned to their size. Initially that means everythi
116.
by gchadwick 3y ago
We've had people consider Ibex for space applications, well verified and has a dual-core lockstep option: https://github.com/lowRISC/ibex . An ETH Zurich team have done a triple core lockstep version for cubesats:
117.
by gchadwick 3y ago
This may add a bit of colour to a technical debate going on right now in the RISCV Profiles working group. Qualcomm have proposed dropping the C (16-bit compressed instructions) extension from the RV23A profile (effectively the set of thing
118.
by gchadwick 3y ago
It's also just quicker turning up 1h30 early for a Eurostar is very early, turning up 1h30 early for a plane can be a bit tight.
119.
by gchadwick 3y ago
Doing a proper fair comparison of microarchitectures is incredibly difficult. Even measuring the the power consumption of the core alone may be rather tricky. Especially if you don't have access to the design details. So when it says &
120.
by gchadwick 3y ago
CPU verification is generally done at a number of levels. For the A510 we had a block level test suite for the L1 memory system. This runs in a RTL simulator (provided by commercial EDA tool vendors, Cadence Xcelium, Synopsys VCS and Mentor

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