CPU verification is generally done at a number of levels. For the A510 we had a block level test suite for the L1 memory system. This runs in a RTL simulator (p

CPU verification is generally done at a number of levels. For the A510 we had a block level test suite for the L1 memory system. This runs in a RTL simulator (provided by commercial EDA tool vendors, Cadence Xcelium, Synopsys VCS and Mentor/Siemans Questa are the big 3). This is good for testing detailed behaviour in particular weird corner cases that are hard to produce. As a design engineer this is generally your primary verification environment. Then you have top-level/system-level. Here you're running full programs on the CPU alone or on the CPU in a wider system simulation. There's multiple ways to run this simulation. Again you can use RTL simulations, the major disadvantage is these will be very slow (think on the order of 1-10 kHz). You can use an FPGA, this has the advantage of speed but limited design visibility (an RTL simulation can provide you with a complete dump of what every signal is doing at every clock, in an FPGA you have to explicitly add an internal logic analyser to look at a limited selection with a limited time window). Finally you have emulators, special purpose super computers for RTL simulation effectively. These are fantastic, you can get good speed (1 MHz order of magnitude) and design visibility closer to RTL simulators than FPGA. The downside here is cost, they are very very expensive (think $1 million starting point). At Arm all of the above techniques were used.