brigade

24 ms·

271.
by brigade 4y ago
As much as you can't afford a home in the US, you wouldn't be able to afford to buy a home in Europe even harder.
272.
by brigade 4y ago
No, gcc added support for ABIs that defined long as 8 bytes. They didn't change the size of long for any ABI.
273.
by brigade 4y ago
Vroom and Carvana are shit with mechanical inspections/repairs, but CarMax should be fine; unlike Vroom/Carvana their in-house mechanics operate basically identically to the service center of other dealerships. Also they actually
274.
by brigade 4y ago
No; the dealer license allows them to own cars without titling them in their name, not escape the sales tax / registration the state collects when a car is titled. And that car was titled, just as every Tesla is after Tesla sells it.
275.
by brigade 4y ago
RISC-V's core philosophy, with V masks and elsewhere, is to make the smallest and simplest possible implementation as simple and small as possible (in this case, re-using the vector register file for masks reduces the minimum register
276.
by brigade 4y ago
> the inherent absence of some patents required for the standard/implementation to function in initial patent pool I guess this is the disconnect; AOMedia worked very hard during standardization to avoid infringing existing patents
277.
by brigade 4y ago
So which company is large enough to have patents that supposedly are essential to AV1 despite not participating in the process, is small enough that AOMedia overlooked those patents during the standardization process, yet is large enough to
278.
by brigade 4y ago
If they don't have to license AV1 patents, then how exactly are they being strong-armed into granting licenses to their own patents?
279.
by brigade 4y ago
...is the argument that these companies that didn't participate in the development of AV1 now can't avoid using AV1, and thus are forced to license essential AV1 patents under the terms offered? (so, is the EU also saying that onc
280.
by brigade 4y ago
You can read it for yourself - https://aomedia.org/license/patent-license/ First, near as I can tell, they only claim you need a patent license if you distribute an encoder/decoder. MPEG-LA has claimed distri
281.
by brigade 4y ago
It's royalty free, not patent free. If AOMedia had no applicable patents, the patent license under issue wouldn't exist.
282.
by brigade 4y ago
AMD and Intel chips take ~5 years from starting work to being available to buy The architecture is basically frozen 2 years before tapeout, which itself is a year before they go on sale.
283.
by brigade 4y ago
Search history including Google search history, I’ve found. I also completely believe that YouTube correlates via IP for at least not-logged-in views (or at least tries to associate to accounts even if they've never logged in); I get b
284.
by brigade 4y ago
https://support.apple.com/en-us/HT201236 or https://support.apple.com/guide/mac-help/view-and-edit-files... I guess? First one also mentions the ⌘-click on a window's title
285.
by brigade 4y ago
> (even if they can actually execute all instructions concurrently, which is not clear to me and unlikely - Intel can also only execute some instructions on certain ports) It's pretty symmetrical, moreso than Cortex-X2's 4 pipe
286.
by brigade 4y ago
Tesla's isn't good enough to replace wheel torque as an attention monitor, and they don't even pretend to (still requires wheel torque to keep FSD/autopilot enganged.) In particular, it has terrible night vision and no I
287.
by brigade 4y ago
Is AX88178 compatible without 3rd party drivers? Plugable says no, and IIRC I needed a driver that never got updated for my gigabit ASIX, but it might been a slightly different chipset... At any rate, a big issue is that for USB, macOS only
288.
by brigade 4y ago
If something is bound by memory/cache bandwidth, then increasing ALU width wouldn't help in the first place.
289.
by brigade 4y ago
Yeah that's NEON. And there's instructions that literally calculate SHA256 so generalizing that is moot. My point was first, what real benchmarks are there of SVE2's benefits over NEON with mainstream CPUs that M2 would compe
290.
by brigade 4y ago
Soo... basically a 2x speedup in going from 4x128b to 2x512b ALUs, after discounting the frequency difference. But realistically, Intel's client configurations are 3x256b, which is only 25-40% faster in that paper. (I suspect any appli
291.
by brigade 4y ago
Android flagships are shipping with SVE2 as of this year, which I actually didn't realize until like two weeks ago because there's been nearly zero buzz about it. What's SVE2 being used for over NEON as of now?
292.
by brigade 4y ago
Emulation of an x86 kernel level means you lose the hardware-assisted virtualization support you'd get with an ARM kernel, and emulating an MMU is slow (among other things.) Technically this would be replacing QEMU user-mode emulatio
293.
by brigade 4y ago
It's one of the oldest widespread applications of neural networks for video, with NNEDI at least dating to 15 years ago. That said, I don't think there's been much work incorporating new research from the current resurgence o
294.
by brigade 4y ago
You might be confusing infringement with patentability. If an independent claim isn't infringed, then by extension none of the dependent claims are infringed and they don't have to be considered. So the easiest route to defending
295.
by brigade 4y ago
Most reasonable IMO would be a hypothetical AVX-256 that was AVX-512 minus ZMM registers. Intel chose against that. So the only reasonable options for a big little system are: 1. Not have a big little system. But little cores are quite usef
296.
by brigade 4y ago
Depends on what you consider reasonable. Worst case is 512-bit vpermi2*, which could be implemented with 16x 128-bit vpermi2-like uops, if the needed masking was implicit. Which to me is reasonable for ISA compatibility. (Also considering t
297.
by brigade 4y ago
You don’t need larger than the 128-bit ALUs or the 207x128-bit register file Gracemont already has to implement AVX-512. It doesn’t make sense on its own with that backend, but for ISA compatibility with a big core it does.
298.
by brigade 4y ago
Xuantie 910 has 2x128b ALUs, which is kinda my point that the decoding of RISC-V vector instructions to uops is more complex than it needs to be, because it depends on the value of user-settable registers. XT-910 also highlights that with t
299.
by brigade 4y ago
How do you handle LMUL>1 without "looping" across the multiple destination registers?
300.
by brigade 4y ago
Specifically, the M1's NEON ALUs can handle 64 bytes per cycle on the big cores. Most Cortex can only do 32 bytes per cycle (Cortex X1/X2 is the exception), and the lower end designs are only 16B/cycle. Plus the pmull+eor fus

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