RISC-V's core philosophy, with V masks and elsewhere, is to make the smallest and simplest possible implementation as simple and small as possible (in this case

RISC-V's core philosophy, with V masks and elsewhere, is to make the smallest and simplest possible implementation as simple and small as possible (in this case, re-using the vector register file for masks reduces the minimum register file needed by 3%.) Even if it's at the expense of bigger cores needing to have additional logic to fix up the performance implications, and adding possible pitfalls like having to know what triggers a CPU switching its interpretation of v0 between "mask" and "vector". This certainly has its place; there are way more tiny ARM cores running various bits of firmware in a typical computer than big cores running OS/application code. But way more programmers write code that runs on those big cores, and to be rude, a lot of the fixups RISC-V expects of big cores feel exactly like the workarounds Intel needed to implement as CPUs became faster and more complicated, at least to me. Except Intel has the excuse that x86 dates back to the 70's so unlike RISC-V it wasn't designed with that expectation. Well, even ARM was designing new features with performance pitfalls in high-performance CPUs into the 2000's... (NEON 32/64-bit register views overlapping with the high bits of larger registers, and permute instructions with two destructive outputs, both of which were fixed in arm64)