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You don’t need larger than the 128-bit ALUs or the 207x128-bit register file Gracemont already has to implement AVX-512. It doesn’t make sense on its own with t
by brigade 4y ago
You don’t need larger than the 128-bit ALUs or the 207x128-bit register file Gracemont already has to implement AVX-512. It doesn’t make sense on its own with that backend, but for ISA compatibility with a big core it does.
- Dylan16807 4y agoCan the shuffling instructions be reasonably efficient with a small ALU?
- brigade 4y agoDepends on what you consider reasonable. Worst case is 512-bit vpermi2*, which could be implemented with 16x 128-bit vpermi2-like uops, if the needed masking was implicit. Which to me is reasonable for ISA compatibility. (Also considering that having to deal with ISA incompatibility across active cores is not reasonable at all.)
- moonchild 4y ago> having to deal with ISA incompatibility across active cores is not reasonable at all If the OS would give me the tools to deal with it, I would find it completely reasonable to write (eg) both avx2 and avx512 kernels to be run concurrently on the same machine.
- jeffbee 4y agoI'm not sure that users would accept that. You could have a situation where an ifunc is resolved on a fast core with a slightly superior AVX-512 definition, but then the thread migrates to an efficiency core and the AVX-512 definition is dramatically slower than what could have been achieved with AVX2 (e.g. if a microcoded permute was 16x slower).
- brigade 4y agoMost reasonable IMO would be a hypothetical AVX-256 that was AVX-512 minus ZMM registers. Intel chose against that. So the only reasonable options for a big little system are: 1. Not have a big little system. But little cores are quite useful for power efficiency in laptops… 2. Don’t support AVX-512 on any cores. Everything beyond AVX2 becomes a dead extension outside of server chips. 3. The little cores support AVX-512 as best as is reasonable. Then thread director can weight AVX-512 usage even heavier than it already weights AVX2. Also AVX2 performance on Alder Lake is already different between the cores enough that optimal implementations can be different.
- jeffbee 4y agoThat makes sense and alludes to my feeling that the big-little thing has been a big mistake. If they come out with an all-big workstation CPU that enables AVX-512 then I am changing to that.