brennanpeterson

7 ms·

31.
by brennanpeterson 3y ago
It is a roughly 20% improvement to speed and power per area. And about 20% density. So you get more, faster cores/units, in the same footprint. sram.is the exception as it scales poorly, so don't expect much. If anything, this is
32.
by brennanpeterson 3y ago
It is? A factory makes transistors ,and if you increase a 'node', you make twice as much. If you do an amazing job, you might reduce cost 10%. So by far the best way to maximize value in semiconductors is to enable shrink. But you
33.
by brennanpeterson 3y ago
The stage, the mirror/aberration control, and metrology (overlay/,reg and height/focus) are massive projects A fair case can be made that the twinscan concept is the key.
34.
by brennanpeterson 3y ago
Having met the guy...he is pretty close to knowing all the bits at a pretty deep level. That is part of the heart of asml, people are expected to know things at a very deep level.
35.
by brennanpeterson 3y ago
It is old school in the sense that it is quite pragmatic. It is aimed at Mainstays of engineering like 'did I improve performance in this line' or 'ate these systems giving the same output's or even 'how do.i design
36.
by brennanpeterson 4y ago
For a very low density experiment and. A few other cases, it is an option. Or for mask writing. It is very informative to consider the data rate. To approximate (and perhaps do bad phone math) lithography tool has ~1bit per 10nm^2, doing 1
37.
by brennanpeterson 4y ago
You have Lam, Applied, and KLA in SV which are 3/5 of the largest equipment suppliers. Along with that the entire supply chain and support. You also have most of your likely customers nearby. So it remains expensive and still a great p
38.
by brennanpeterson 4y ago
Start by not calling it the boring stuff. Atonse's comment is excellent. You can get excellent CFO and government finance help via contractors. But in the end you will want to at the least understand it: what marketing, fundraising, sa
39.
by brennanpeterson 5y ago
I am curious. Are all boards that have equal white and black tiles counts solvable?
40.
by brennanpeterson 5y ago
As a rule of thumb, about 10 unit cells (5nm). There are some exceptions, but this is a useful number. That means that practically, the smallest conceivable metal pitch is 10nm, the smallest gate is 20. From 5nm, it implies a factor of 10 i
41.
by brennanpeterson 5y ago
Masks are not whole wafer , except in some packaging cases. The mask illuminates a 25*35 area, for both 300mm and 200mm. Masks are not a significant expense for most processes. Nor is the bare wafer. It is all the process steps that drive t
42.
by brennanpeterson 5y ago
I doubt this is true. Mike Mayberry (Intel) softly announced buried power rail last year, as a 'within 5 years' tech. That suggests it has been prototyped, since from final tests to HVM is at least 2 years. Maybe not great. Within
43.
by brennanpeterson 5y ago
This is true but also wrong. The transistors themselves have a specific operating voltage.
44.
by brennanpeterson 5y ago
Mostly agreed, but I did like the last sentence: sometimes it is easier to solve the general problem than the specific one. That is a useful trick to keep in mind all the time. The point of course, is not to learn to solve integrals, but to
45.
by brennanpeterson 6y ago
Woven metal tires are old. And nitinol is also old (it was not developed for the rover, a wiki check would show as much). But the combination is new. I imagine the conversation went 'hey I am working on chainmail tires' 'aren
46.
by brennanpeterson 6y ago
I have done a little bit of coding: macros, small programs, tool controllers. What kills me is that I can do 90% of what I need using other tools (excel, JMP, imageJ, matlab) and coding mostly makes things take longer. Most of the effort is
47.
by brennanpeterson 6y ago
Capital equipment is even more barren in information. It might be better said that there are sales, development, and operational aspects to product management. You can split this into a product owner, sales interface, and engineering interf
48.
by brennanpeterson 6y ago
Tsmcs r&d spend has been equivalent to Intel's for the last decade. TSMC did a great job, most particularly on EUV introduction. I don't think wall street cares about outsourcing, except as a potential savings. The hollowing o
49.
by brennanpeterson 6y ago
Everything in M1 and everything on Intel 14nm. Go read wikichip. It is there. IEDM just happened, tons of detail there. 3nm, sure, good luck.
50.
by brennanpeterson 6y ago
Intel 14nm is 42/70/52 (fin/cgp/mmp) with a 7.5 track height. HD stamBitcell is 0.05um2 Very restrictive design rules Tsmc 5nm is 27/54/36 with a 6T and 7.T option. More open design rules. HD SRAM cell is abou
51.
by brennanpeterson 6y ago
You are right, I misread 'high bandwidth' as HBM. I was surprised at the cost as well.
52.
by brennanpeterson 6y ago
A good design + a 1 node (15% transistor level benefit) advantage + embedded(ish) HBM. You kind of expect 15-30% benefit in the same design. Whether CPU or bandwidth bound. Some latency bound benchmarks will be at par. It is a perfect hit o
53.
by brennanpeterson 6y ago
Some yes. Often residual carbon will deposit on the surface and change it (depositing a bit of a surface layer. If you do ion beam imaging, you do etch the surface away with each image.
54.
by brennanpeterson 6y ago
This has been said for the history of the ACLU. And there are difficult balances there: do you defend the Nazi March? What if that March includes armed marchers aiming guns at others? Is aiming a gun speech? Or speech the ACLU has interest
55.
by brennanpeterson 6y ago
There are various areas. 3DNAND is a fully 3D design, and scaled reasonably past the limits of 2D. Crosspoint memory is a simplified 3D structure. In logic, people (Unity, for instance) talk about fully 3D, with stacks of transistors layere
56.
by brennanpeterson 6y ago
What is the magic technique? Selective growth and patterning already have precision in the sub angstrom range, over mms of distance. This is what 'TMU' is, when you read an ASML or Lam paper on the topic. Current target is sub nm,
57.
by brennanpeterson 6y ago
Sure! It is a huge mix. ASICs don't, mobile cannot, and you can't really just ignore. But there are also other tricks, like redundant vias, or SRAM spares, which do make 'yield' less listed by defects than it might first
58.
by brennanpeterson 6y ago
I would add lithoguru.vom and the related courses (Chris Mack) as well as semiengineering.com
59.
by brennanpeterson 6y ago
Agreed on binning, but all DRAM and all NAND are fault tolerant. Between all memory, GPU and GPU-like, and CPU....I have all but mobile, or about 70% of the market.
60.
by brennanpeterson 6y ago
Yes, and I believe TSMC does. Because the dose scales as resolution to the 4th power (or so), it is better to double pattern than to try to single pattern at massive dose. There are also cases where double patterning can reduce defects in s

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