bit-hack

4 ms·

1.
by bit-hack 11mo ago
Thanks for the suggestion, I've added this license to the project.
2.
by bit-hack 11mo ago
The main reason is just due to me knowing my own limitations. SRAM is really simple to interface with and i've not yet tried to write a DRAM controller since its much more complex. Putting SRAM on the board made me more confident about
3.
by bit-hack 11mo ago
Thats an oversight on my part, I should put a license on it. I would love for anyone to be able to build one or tinker with the code as they want to. After all I was only able to make this because others shared their projects that I could l
4.
by bit-hack 11mo ago
The bus controller was fairly straight forward. I found the timing diagrams in the V20 datasheet to be pretty easy to follow. The clock for the CPU is generated by the FPGA which I derived from a clock running at twice the speed, that made
5.
Show HN: FPGA Based IBM-PC-XT(bit-hack.net)
6 points by bit-hack 11mo ago|1 comments
6.
by bit-hack 3y ago
a busy loop waiting for an interrupt to fire?
7.
by bit-hack 4y ago
Oh fantastic! this makes me super happy to hear :) I'd love to play with it.
8.
by bit-hack 4y ago
You mention that you have traced out every transistor from die photos, and I was wondering how much work there would be to make a netlist for the 8086 like that which was used to produce the visual 6502 simulator? It that feasable or is the
9.
by bit-hack 4y ago
What I'm curious about is how this has been done. I don't think that the source for UT99 has been released, so does icculus have access to the source and has then ported it to emscripten, or has it been decompiled from x86 and th
10.
by bit-hack 5y ago
This is great, I've been wanting an ISA card with an FPGA on it for a long time so that I can experiment. I've ordered a few of these PCBs to build some myself. Its very kind of the author to give the design away for free. I als
11.
by bit-hack 5y ago
I've honestly never seen .C used in the wild. I imagine anyone whose written a bit of portable code would immediately realize this is a bad idea.
12.
by bit-hack 6y ago
Its still blows my mind that he fit this in ~1k LUTs. I'm new to FPGA but the closest I got was about 4.5K LUTs for a comparable core. I wish there were more easy to access material about timing and size optimization for FPGA.
13.
Show HN: A small RISC-V Virtual Machine(github.com)
2 points by bit-hack 6y ago|0 comments