baobrien

15 ms·

121.
by baobrien 9y ago
PCI Express works more like Ethernet than classic PCI or a parallel bus like Wishbone. There's no per-bit (or even per-byte) handshaking between devices; they communicate with packets over a longer time span.
122.
by baobrien 9y ago
I have a DOS-based LeCroy oscilloscope with an embedded 386 and an IDE hard drive. The 'oscilloscope' part is hooked up through an ISA card.
123.
by baobrien 9y ago
Elliptic Curves are one of the core mathematical constructs behind most of the commonly used non-RSA asymmetric cryptographic algorithms (curve25519, ed25519, ECDH, ECDSA).
124.
by baobrien 9y ago
UC Berkeley has had functional RISC-V silicon for years now as research devices. RISC-V hasn't really been a thing outside of their architecture research group for more than a few years now. The UCB-BAR also has some fairly decent RISC
125.
by baobrien 9y ago
Also no explicit register move instruction, it's ADDI rd,rs1,0. NOP is ADDI x0,x0,0.
126.
by baobrien 9y ago
I don't think mosh is just an SSH wrapper. IIRC, it uses SSH to start a mosh session on the server side, but from there it uses it's own UDP based protocol to sync the terminal 'framebuffer' instead of sending character
127.
by baobrien 9y ago
and it transfers around 70-80Mb if you let the background montage play through
128.
by baobrien 10y ago
I think the RISC-V cores they're putting on their chips are more for management than as application processors. If they didn't use RISC-V there, it'd probably run one of their own ISAs rather than ARM.
129.
by baobrien 10y ago
eh, well designed CSPRNGs are a thing. If they re-seed/add to the entropy pool of the machines on the LSBs of microsecond button timing or something like that, it'll be pretty difficult to influence or predict the outputs.
130.
by baobrien 10y ago
AFAIK, It's intended as a general purpose processor.
131.
by baobrien 10y ago
The FE310-G000 is TSMC CL018G 180nm
132.
by baobrien 10y ago
I think they're using the FT2232H for JTAG as well as serial, so you'd have to do a bit more than replacing the serial port.
133.
by baobrien 10y ago
Also, check out chapter 2 of this paper for the technical and licensing motivation to not go with SPARC or several other RISC ISAs: https://people.eecs.berkeley.edu/~krste/papers/EECS-2016-1.p...
134.
by baobrien 10y ago
For one, MIPS32 and SH2 are both 32-bit ISAs. Extending them to 64-bit would require just as much compiler re-working as building a new RISC ISA -- and it'd no longer be MIPS32 or SH2 anyway.
135.
by baobrien 10y ago
Keep in mind, the UltraSPARC T1 and T2 are only two cores suited to specific workloads. They'd still be starting from scratch on the RTL if they wanted to do anything different with the microarchitecture. Now they've (UCB-BAR anyw
136.
by baobrien 10y ago
I think they mean that the decimal floating point extension ('L') isn't in the spec. Check out the user ISA v2.1. The 'L' name is reserved, but it's not fleshed out.
137.
by baobrien 10y ago
That talk is entirely baseless fear mongering. Electromagnetic Hypersensitivity is entirely unsupported by the science.
138.
by baobrien 10y ago
The linked talk is also TEDx -- even less vetting than normal TED.
139.
by baobrien 10y ago
The UniFi stuff isn't stand alone, but it doesn't need to 'phone home' to Ubiquiti. There's a little management server with a web config interface you need to set up to run everything. It runs on your local network
140.
by baobrien 10y ago
Check out the BOOM RISC-V core. It's a superscalar out of order core from the UCB-BAR that claims similar coremark/Mhz to Arm Cortex-A15 in about half the area. See page 43 - https://riscv.org/wp-content/uploa
141.
by baobrien 10y ago
Queen Victoria died in 1901 and most of the empire was still part of the empire by then.
142.
by baobrien 10y ago
I'd love to see a combined FreeBSD jail and bhyve manager. Can libvirt do that?
143.
by baobrien 10y ago
Transistors built on GaN and SiC processes can operate with a junction temperature of up to around 200C. As you say, that's a pretty big deal for RF power transistors, as they can dissipate quite a lot more power without blowing up. An
144.
by baobrien 10y ago
IEEE papers are also on sci-hub.cc
145.
by baobrien 10y ago
The FPGA disk emulator/interface isn't quite working yet. http://www.righto.com/2016/09/restoring-ycs-xerox-alto-day-7...
146.
by baobrien 10y ago
DJB is still skeptical of Quantum Key Distribution. https://sidechannels.cr.yp.to/qkd/holographic-20160326.pdf
147.
by baobrien 10y ago
That's why I'm a fan of the RISC-V compressed ISA extension. Compressed instructions are 16 bits long and a subset of the 32 bit instructions, but can be mixed freely with 32 bit. The extension also relaxes the alignment requireme
148.
by baobrien 10y ago
This isn't always the case. Check out the RISC-V compressed extension. It turns out that RV64GC usually beats x86_64 on dynamic code size. See slide 31: https://riscv.org/wp-content/uploads/2016/07/T
149.
by baobrien 10y ago
In the case of RISC-V, the compressed extension only covers a subset of the full length instructions, but can be freely intermixed with them. It turns out that RV64GC (risc-v 64 bit with compressed instructions) usually beats x86_64 in dyna
150.
by baobrien 10y ago
The heads in an HDD don't actually touch the surface, they ride on the layer of gas above the spinning platters.

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