> Nothing like it can be done for an x86 cpu. The way modern x86 handles this is typically with a uop cache. But this costs a lot of power, area and only provid

> Nothing like it can be done for an x86 cpu. The way modern x86 handles this is typically with a uop cache. But this costs a lot of power, area and only provides full decode width for a relatively small pool of insns -- 4k on modern Zen, for example. The µOP cache is actually not an explanation of how x86 machines perform the decode, it is rather a way to bypass the decode which is expensive and difficult for them. And the most difficult part is not really the decoding in macro op, the difficulty is to find the boundaries of the instructions to be decoded in parallel. Because the alignment of each instruction to be decoded depends on the size of the previous instructions, this is a sequential process. For example, one way to do this is to use instruction size prediction. Intel and AMD hold several patents related to instruction length prediction [1]. [1]: https://patents.google.com/patent/US20140281246A1/en https://patents.google.com/patent/US20140281246A1/en