avianes

22 ms·

121.
by avianes 6y ago
So you're not talking about the area of the cores, you mean simply bigger in a microarchitectural sense ? Because as I just added in my previous comment (sorry, I don't expect you to reply so quickly) on the dieshots Firestorm cor
122.
by avianes 6y ago
> Apple's core is simply the biggest core on the market. Have you any source to confirm this? Did you include the L1I and L1D cache? Looking at dieshots, Zen2 cores seem easily twice as big as Firestorm cores. But if you have more r
123.
by avianes 6y ago
> There are many issues in determining what is code, where are the branch destinations in case of indirect branches, etc. Yes, handling indrect branch seems a bit complex and I'm not a specialist in the field. But I'm pretty su
124.
by avianes 6y ago
It seems to me that the correct term is "Static Binary Translation" (SBT) for what you call "ahead of time binary translation". And the correct term for "JIT-based emulation" is "Dynamic Binary Translation
125.
by avianes 6y ago
That's a very good lectures! However, there is one thing is regrettable to me in lectures that talks about the micro-architecture of superscalar processors: they never talk about the register bank micro-architecture. The focus is alwa
126.
by avianes 6y ago
RISC-V spec is not yet finished. Currently only the most basic extensions are available. But nothing prevents RISC-V from introducing in the future an extension that extends the conditional code or an extension for integer/float overfl
127.
by avianes 6y ago
> Same instruction (JALR) used for both calls, returns and register-indirect branches (requires extra decode for branch prediction) JALR for call and return used the same opcode but are two different instructions, there is no need for &q
128.
by avianes 6y ago
> If there's an error in e.g. floating-point unit, it would just cause random errors in the output, but the game would probably keep running The processor circuitry does not only consist of transistors dedicated to the datapath, a s
129.
by avianes 6y ago
To me, your example is not really easier to understand than the defer version. The complete flow is immediately apparent in your example, but the "effective" flow (the two malloc and the mutex) is harder to identify. And now imagi
130.
by avianes 6y ago
> So long as you're not using this technique to unlock mutexes, you'll be fine. This does not sound good. In addition, it is worth mentioning that your hack will probably break the return stack buffer of the x86 superscalar pro
131.
by avianes 6y ago
I would be highly curious for more information on this subject. Do you have any sources/information related to thermal cycling damage to cobalt wires or COAG?
132.
by avianes 6y ago
That's a good question ! But I can't give you a accurate answer. In my post I didn't elaborate on thermal dissipation issues because I think there are already enough problems with geometry and routing. But heat dissipation is
133.
by avianes 6y ago
The switch to FinFET is already a use of the 3rd dimension. The channel is moved vertically to reduce the surface area of the transistor. GAAFET are also using the 3rd dimension. But these are uses of the 3rd dimension within the transistor
134.
by avianes 6y ago
> The problem RISC-V faces is that one or more companies start to grow a significant market with non-compliant chips, basically the browser war scenario. The CPU market today is even more closed to competition than web browsers. RISC-V d
135.
by avianes 6y ago
If you need both performance and a small core (and not a superscalar one, because there are small superscalar cores). I will definitely not recommend you to use a RISC-V, RISC-V is not designed for that at all. You should rather turn toward
136.
by avianes 6y ago
I never claimed that RISC-V was ready to go in production. The RISC-V spec is not finished yet. A lot of pieces are still missing to make a serious ARM or x86 competitor.
137.
by avianes 6y ago
You are right, I didn't answer to your point. So I'm going to complete my thought. I explain that RISC-V removes unnecessary complexity from the hardware and puts this unnecessary complexity on the software. All they did was move
138.
by avianes 6y ago
> I see that you do not understand that an emulated popcount instruction would be worse than useless. Where do you read that I'm talking about emulating popcount in software? I mean exactly the opposite. If you need to support all B
139.
by avianes 6y ago
Yes, only standard extensions will be supported by all compilers. Why is this a problem? If a company needs to design its own extension for its specific application, RISC-V allows it. And it will never get upstream, because it is only relev
140.
by avianes 6y ago
I don't really understand your comparison with linux distros. Of course extensions will be fragmented, each chip will only embed a faction of the ISA according to its range of application. But Linux distro are not made to be "modu
141.
by avianes 6y ago
> RISC-V is designed to the momentarily fashionable idea that status flags are a big hurdle in optimizing instruction sequencing. > Modern cores rename status flags along with all the other registers, making them cheap. The RISC-V is
142.
by avianes 6y ago
> Manifestly, the B extension isn't in any of the chips being produced now The RISC-V chips produced today are not made for performance or be competitive, they are proof of concepts, toys and prototypes. The current state of the RIS
143.
by avianes 6y ago
I agree that the transition to RISC-V (if it's going to happen) will take time, I do not agree that it will take even longer for the B extension. That's why I disagree with him.
144.
by avianes 6y ago
Frist, we are talking about RISC-V. The ISA is not finished. So yes, it will take time, but that's not the point. > How long until that instruction is available in all chips that are manufactured? Longer. The author didn't say
145.
by avianes 6y ago
> it won't be in the smaller chips, or even in the biggest ones for a good while. Where does this statement come from? Do you have any sources or arguments to justify that?
146.
by avianes 6y ago
> For advanced designs the instruction set really doesn't matter that much I disagree. For high performance applications some extensions are required. That's why x86 has so many extensions such as AVX.
147.
by avianes 6y ago
The RISC-V spec is not finished yet. RISC-V is a modular ISA, the base ISA contains only the minimum that must be included for all architectures. The basic ISA therefore excludes multiplications, divisions, float, atomic, SIMD, etc. The bas
148.
by avianes 6y ago
> Why are you treating Lenovo and Thinkpad separately? They're the same company, even if there's some internal separation (that Lenovo can violate as they wish). Because historically they are two different entities. Lenovo acqu
149.
by avianes 6y ago
> That's putting a lot of faith into internal separation of departments for a company with a track record of inserting malware into their products and lying about it. 1) Why would a pre-installed Ubuntu from Lenovo be more risky tha
150.
by avianes 6y ago
No, it's not really the same Lenovo. Thinkpad & ThinkStation never had superfish pre-installed. The development of Thinkpad products is separated from the development of other Lenovo products.

More ›