adapteva

7 ms·

31.
by adapteva 3y ago
The swappable nature of the chiplet bricks was meant to convey that they are the equivalent of toy plastic blocks. We didn't disclose the standard yet, this will be coming soon. The RISC-V chiplet a standard RV64GC. The high level spec
32.
by adapteva 3y ago
No my bad for not being clear. If all you want is a bunch of LUTs then the high end fpga is the right answer. FPGA today is a lot of other things besides PL (serdes, cpu, DSP, ML, DDR IF...) and some of those features are only available on
33.
by adapteva 3y ago
Thanks for the feedback. The access mechanism will be adjusted going forward. This was my bad.
34.
by adapteva 3y ago
Each chiplet comes with its own tool chain. The FPGA has a full RTL2BITS tool chain, the CPU is supported by standard RISC-V tools, and the ML chiplet will have a typical ML programming flow. The full system parallel heterogeneous programmi
35.
by adapteva 3y ago
Depending on who you ask, the silicon area overhead of programmable logic FPGA is 25X-100X compared to hard coded logic of an ASIC (at the same node). Very few applications can afford the cost of full platform programmability with large dev
36.
by adapteva 3y ago
If a catalog low performance $1 mirocontroller is good enough, then it's probably the right answer. A low cost FPGA (~$5) with an embedded CPU is also a great choice. If none of the off the shelf components can meet the application cos
37.
by adapteva 3y ago
Do folks prefer FB?
38.
by adapteva 3y ago
No relation. Zero ASIC predates Matt Venn's "Zero To ASIC" course. We made some announcments on Twitter and LI in 2020 to announce company formation, but Matt didn't see them. I agree that the name collision is unfortuna
39.
by adapteva 3y ago
ASICs are very diverse with many dimensions and it depends on the definition. Pure ASICs like bitcoin miners are very rare. Most "ASICs" are generally on the programmable platform spectrum (apple socs, snapdragon, versal, ML start
40.
by adapteva 3y ago
Thank you!
41.
by adapteva 3y ago
Thanks for the feedback! Since our business model is b2b and we are giving away emulation time on some very expensive cloud FPGAs, we figure the automated linkedin auth was fair. With Parallella we had 10K mostly anonymous customers and for
42.
by adapteva 3y ago
Great question! Not ready to announce our protocol yet. Coming soon....
43.
by adapteva 3y ago
Structured ASIC are generally fixed size monolithic chips with metal/via programmablity to control some amount of wiring (hardcopy, easic,..). Modern FPGAs with a mix of har coded blocks (serde, cpus, DSP) connected by NoCs and PL is a
44.
by adapteva 3y ago
Thanks! Yes, we are focusing on big digital because that's where the big cost problem is. Also, the kind of block based design we are proposing requires a standardized interface. Th standard interface för analog is "a wire".:
45.
by adapteva 3y ago
This is probably not the place to write a full post-mortem, I will save that for a blog post or something, but here are a few points: * 2008 was a really bad time to launch a chip startup * Epiphany predated RISC-V...nobody wants a new ISA
46.
by adapteva 3y ago
Yeah, I have been struggling with these questions for 25 years and I am not alone.:-) You can always spend $100M and build exactly what you need (eg. 16 RISC-V processors with custom vector extensions and a selection of I/), HBM3, serd
47.
by adapteva 3y ago
True
48.
by adapteva 3y ago
Code(RTL, Chisel, C) that can be bundled as a memory mapped IP and turned into a brick integrates really well. The problem is that this reqyuires custom tooling. A full mask set taoeout is going to cost $5M-$10M and take 6 months to complet
49.
by adapteva 3y ago
The challenge with today's FPGAs is that you rarely get exactly what you need. The smalle ones aren't feature complete and the big ones are expensive and power hungry. Lots of questions though, which interface parts are you talkin
50.
by adapteva 3y ago
Yes, you are right that pseudo-integrated silicon-photonics is really exciting! The Ayar Labs + Intel FPGA chiplet combo based on AIB is a great example. Packaging is one of the really big challenges, DARPA invested ~$100M to solve this pro
51.
by adapteva 3y ago
It's a 4x4 array of chiplets, the rest is UCIe/IO logic. the ebricks do have some pass throughs, but real IO capability is done through UCIe based chiplets.
52.
by adapteva 3y ago
This is Andreas Olofsson at ZA, ama...
53.
by adapteva 3y ago
Cerebras is the anti-chiplet approach, working at the wafer scale stitching together reticle sizes islands of logic using on wafer wiring.
54.
by adapteva 3y ago
As long as the processing is being being done with electrons (CMOS), there will be a pretty big hit for converting back and forth to photons. In package chiplet communication is actually not that inefficient as long as you can put them righ
55.
by adapteva 3y ago
If an FPGA can get the job done, it's usually the right answer. However FPGA programmability comes with a 25x-100x penalty in terms of area, cost, power, performance compared to application specific devices. Sometimes 100x matters...
56.
by adapteva 3y ago
Agreed...although not sure if it's any more impressive than automated fabs that churn out nanometer precision transistors with billion transistors chips costing less than a cup of coffee per chip.:-)
57.
by adapteva 3y ago
The current leading edge processing products moved to chiplets because it was the optimal/only solution from a cost and performance perspecitve. If we assume that reticle sizes will stay roughly similar and process scaling will continu
58.
by adapteva 3y ago
Not sure what your friend is referring to, but packages with exposed dies are definitely more fragile than ones with built in heat sinks.
59.
by adapteva 3y ago
The best chips TODAY use chiplets. Check out Epyc, Ponte Vecchio, all high end GPUs and ML accelerators using HBM memory. A chiplet is generally defined as a chip/die with custom interfaces for in package communication.
60.
by adapteva 3y ago
Yes, here have been a fair number of public DoD studies around the virtues of disaggregation when it comes to security. Minimize the people/things you have to trust (eg. RoT).

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