3 ms·
It's a 4x4 array of chiplets, the rest is UCIe/IO logic. the ebricks do have some pass throughs, but real IO capability is done through UCIe based chiplets.
by adapteva 3y ago
It's a 4x4 array of chiplets, the rest is UCIe/IO logic. the ebricks do have some pass throughs, but real IO capability is done through UCIe based chiplets.
- addaon 3y agoThanks. I'm trying to think of cases where (assuming no use of the AI stuff) this actually ends up cheaper/smaller than just embedding 16x a tile's compute cores (or a smaller number of much higher performance cores) and 16x a tile's FPGA fabric... with such a small number of options and small number of tiles, I'd suspect (but could easily be wrong) that the area overhead for bonding is on the same order of magnitude as the actual logic here. And while having a large number of fast cores scattered through FPGA fabric would be /relatively/ novel, it seems like it would support the type of flexible configurability that's needed here. I could imagine that this grows in power with a growing ecosystem of tiles, but I'm stretching my mind here for tiles that actually need to be ASICs instead of just implemented in fabric.
- adapteva 3y agoYeah, I have been struggling with these questions for 25 years and I am not alone.:-) You can always spend $100M and build exactly what you need (eg. 16 RISC-V processors with custom vector extensions and a selection of I/), HBM3, serdes, ...). If you are lucky your with your application fit (cost, power, performance) you could possibly buy a Snapdragon, Xavier, Versal, Agilex. The problem we are addressing is the gap, where you don't have $100M in your pocket and you are constrained by physics (size, weight power) or cost.