_mouvantsillage

4 ms·

1.
by _mouvantsillage 4y ago
I think that you could check Sozi: https://sozi.baierouge.fr A big rewrite of its documentation is in progress at: http://sozi.guide I have been developing it since 2009 and I think it has become a nice and fun tool
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by _mouvantsillage 5y ago
Because Jupyter originates from the IPython project, hence the ipynb (IPython NoteBook) extension. IPython initially was a monolithic project that offered the notebook interface and the Python kernel in a single release. When the notebook i
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by _mouvantsillage 5y ago
Changing username is allowed. You just need to ask by e-mail (see https://news.ycombinator.com/newsfaq.html ). I did it a few weeks ago and the change was effective a few hours later.
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by _mouvantsillage 5y ago
Now I think I understand what you mean. For many hardware engineers, I think that the message-passing semantics is a conceptual framework for explaining how simulators work. It is considered as a "necessary evil" that must be take
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by _mouvantsillage 5y ago
While simulation is a well-established practice among digital hardware developers, I have the impression that formal verification is still largely ignored. I hope it changes as free tools are emerging such as SymbiYosys https://s
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by _mouvantsillage 5y ago
My experience in the lower-level aspects of hardware synthesis is limited but I would love to explore this topic. I use proprietary synthesis tools for FPGAs everyday but I do not develop them. My situation is similar to that of a software
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by _mouvantsillage 5y ago
Author here. This post is part of an ongoing experiment to use Racket as a platform for hardware description languages. Describing a RISC-V core in Racket is a step in this direction, but the ultimate goal is neither to use Racket itself as
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Show HN: A RISC-V core in Racket(guillaume.baierouge.fr)
122 points by _mouvantsillage 5y ago|27 comments