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AMD's Ryzen 9 9950X3D2 Dual Edition crams 208MB of cache into a single chip
- Readerium 7mo agoCan someone explain if the 3D Vcache are stacked on top of each other or side by side. If they are stacked then why not 9800X3D2?
- zdw 7mo agoThe 99xx chips have two CPU dies, and one cache die is on each CPU die.
- modeswitch 7mo agoThe 3D V-Cache sits underneath only one of the CCDs. See https://en.wikipedia.org/wiki/Ryzen#Ryzen_9000 https://en.wikipedia.org/wiki/Ryzen#Ryzen_9000.
- deleted 7mo ago[deleted]
- Tostino 7mo agoDid you forget which thread we are on?
- modeswitch 7mo agoOh heh, I thought they were asking about the X3D. My bad ><.
- anonymars 7mo agoThat's what's different about this one. "Enter the Ryzen 9 9950X3D2 Dual Edition, a mouthful of a chip that includes 64MB of 3D V-Cache on both processor dies, without the hybrid arrangement that has defined the other chips up until now."
- deleted 7mo ago[deleted]
- chao- 7mo agoCrazy to think that my first personal computer's entire storage (was 160MB IIRC?) could fit into the L3 of a single consumer CPU! It's probably not possible architecturally, but it would be amusing to see an entire early 90's OS running entirely in the CPU's cache.
- bombcar 7mo agoIIRC some relatively strange CPUs could run with unbacked cache.
- twbarr 7mo agoIntel's platform, at the very least, use cache-as-ram during the boot phase before the DDR interface can be trained and started up. https://github.com/coreboot/coreboot/blob/main/src/soc/intel/common/block/cpu/car/cache_as_ram.S https://github.com/coreboot/coreboot/blob/main/src/soc/intel...
- cwzwarich 7mo agohttps://github.com/coreboot/coreboot/blob/main/src/soc/intel/common/block/cpu/car/cache_as_ram.S https://github.com/coreboot/coreboot/blob/main/src/soc/intel...
- wmf 7mo agoContext: Early in the firmware boot process the memory controller isn't configured yet so the firmware uses the cache as RAM. In this mode cache lines are never evicted since there's no memory to evict them to.
- lathiat 7mo agoI remember the talk about the Wii/WiiU hacking they intentionally kept the early boot code in cache so that the memory couldn’t be sniffed or modified on the ram bus which was external to the CPU and thus glitchable.
- coppsilgold 7mo ago
- qmr 7mo ago[flagged]
- renewiltord 7mo agoI have a gigabyte of cache on my 9684x at home!
- nexle 7mo agoBreakdown of the (semi-clickbait) 208MB cache: 16MB L2 (8MB per die?) + 32MB L3 * 2 dies + 64MB L3 Stacked 3D V-cache * 2 For comparison, 9950X3D have a total cache of 144MB.
- teaearlgraycold 7mo agoI wouldn’t be caught dead with less than 200MB of cache in my desktop in 2026.
- trynumber9 7mo ago> 16MB L2 (8MB per die?) It is indeed 8MB per compute die but really 1MB per core. Not shared among the entire CCD.
- magicalhippo 7mo agoProbably fun for those who already bought DDR5 memory... still kicking myself for not just pulling the trigger on that 128GB dual stick kit I looked at for $600 back in September. Now it's listed at $4k... Meanwhile I hope my AM4 will chug along a few more years.
- jofzar 7mo agoI really want a x3d because a game I play is heavily single threaded, I have the income and the financial stability but I can't in any good conscious upgrade to am5 with the ram prices. It's insane
- magicalhippo 7mo agoYep exactly the same situation. I would not be surprised if we see casualties in adjacent markets, such as motherboards, coolers and whatnot.
- fakwandi_priv 7mo agoAMD had an upgrade path with the 5700x3d, assuming you’re on AM4. Just reading now that they went out of production half a year ago which is a shame. I was very impressed being able to upgrade with the same motherboard 6 years down the line.
- timschmidt 7mo agoI'm the mythical customer who went from a 1700X in a B350 motherboard near launch day to a 5800X3D in the same board (after a dozen BIOS updates). Felt amazing. Like the old 486DX2 days.
- slightlygrilled 7mo agoSame! Kept checking back for bios updates and even years later they kept announcing more support! Truly crazy. Other than the speed it’s a very good reason to go with amd, the upgrade scope is massive, on am5 you can go from a 6 core and soon all the way to a 24 core with the new zen6
- fc417fc802 7mo agoGiven that the dies still have L3 on them does this count as L4 or does the hardware treat it as a single pool of L3? Would be neat to have an additional cache layer of ~1 GB of HBM on the package but I guess there's no way that happens in the consumer space any time soon.
- trynumber9 7mo agoPer compute die it functions as one 96M L3 with uniform latency. It is 4 cycles more latency than the configuration with smaller 32M L3. But there are two compute dies, each with their own L3. And like the 9950X coherency between these two L3 is maintained over global memory interconnect to the third (IO) die.
- monster_truck 7mo agoThe extra cache doesn't do a damn thing (maybe +2%) The lower leakage currents at lower voltages allowed them to implement a far more aggressive clock curve from the factory. That's where the higher allcore clock comes from (+30W TDP) I'm not complaining at all, I think this is an excellent way to leverage binning to sell leftover cache. Though if I may complain, Ars used to actually write about such things in their articles instead of speculate in a way that suspiciously resembles what an AI would write.
- EnPissant 7mo agoIt's very workload dependent. It certainly does more than 2% on many workloads. See https://www.phoronix.com/review/amd-ryzen-9-9950x3d-linux/10 https://www.phoronix.com/review/amd-ryzen-9-9950x3d-linux/10 > Here is the side-by-side of the Ryzen 9 9950X vs. 9950X3D for showing the areas where 3D V-Cache really is helpful: Coincidentally, it looks they filtered to all benchmarks with differences greater than 2%. The biggest speedup is 58.1%, and that's just 3d vcache on half the chip.
- spockz 7mo agoI think GP was saying that the additional 3D cache on this chip compared to the standard x3d isn’t going to do much. I’m curious to see whether the same benchmarks benefit again so greatly.
- bell-cot 7mo ago> I think GP was saying... Agree. The article's 2nd para notes "AMD relies on its driver software to make sure that software that benefits from the extra cache is run on the V-Cache-enabled CPU cores, which usually works well but is occasionally error-prone." - in regard to the older, mixed-cache-size chips. > I'm curious to see... Yeah - though I don't expect current-day Ars Technica will bother digging that deep. It could take some very specialized benchmarks to show such large gains.
- monster_truck 7mo ago
- erulabs 7mo ago9950X3D2? AMD, who is making you name your products like this? At some point just give up and name the chip a UUID already.
- jofzar 7mo agoI actually don't mind this one, 9950 is the actual chip, x3d is the cache (where it's larger) and the 2 stands for it being on both chiplets.
- sidkshatriya 7mo agoLike your UUID joke but agree with sibling comment that 9950X3D2 is actually a good name.
- hu3 7mo agocan't agree. this name has logical meaning
- throwaway85825 7mo agoIt's disappointing that they had this for years but didn't release it until now.
- stingraycharles 7mo agoI think it’s mostly that they had leftover cache.
- magicalhippo 7mo agoMakes sense. RAM pricing surely has lead to a fall of AM5 high-end CPU purchases, might as well try to get some extra cash from those who still buy. Bin the remaining now non-X3D chips as something else.
- Ekaros 7mo agoBad time to move entirely new platform. Perfect time to sell to upgrade junkies just CPU.
- neRok 7mo agoThis video made the argument that AMD released it to not give Intel a look-in: [AMD KILLED Intel's 290K Dreams w/ R9 9950X3D2](https://www.youtube.com/watch?v=u7SyrDPbKls https://www.youtube.com/watch?v=u7SyrDPbKls)
- stingraycharles 7mo agoI like this theory more, perhaps it’s both.
- tw1984 7mo agothat is larger than the HDD of my first PC.
- jaimex2 7mo agoCan someone like... boot Windows 98 on these on a system with no ram?!
- bell-cot 7mo agoConceptually - yes, easily. But to do it literally - I'm not a low-level motherboard EE, but I'd bet you're looking at 5 to 7 figures (US $) of engineering work, to get around all the ways in which that would violate assumptions baked into the designs of the CPU, support chips, firmwares, etc.
- ggm 7mo agoMake a fake ram which offers write through guarantee and returns bus no matter what address is referenced. You could possibly short circuit any "is ram there" test if it just says yes for whatever size and stride got configured.
- anticensor 7mo agoThe CPU literally initialises itself without DDR then initialises the DDR PHY, there must be a way of keeping the CPU in that "cache as RAM" mode.
- brandnewideas 7mo agoTheoretically anything is possible with enough thought and work.
- rldjbpin 7mo agoor an older version of puppy linux?
- DeathArrow 7mo agoMy first computer had 64KB of RAM. My first PC had 8MB of RAM.
- 2001zhaozhao 7mo agoI don't really see a huge reason to buy this other than it being a top-tier halo product. For gaming, AMD already pins the game threads to the CCD with the extra cache pretty well. For multi-threaded workloads the gain from having cache on both CCDs is quite small.
- adrian_b 7mo agoThe gain is very workload dependent, so there are no generally-applicable rules. There are many applications which need synchronization between threads, so the speed of the slowest thread has a disproportionate influence on the performance. In such applications, on X3D2 the slowest thread has a 3 times bigger cache on an X3D2 vs. X3D. That can make a lot of difference. So there will be applications with no difference in performance, but also applications with a very large difference in performance, equal to the best performance differences shown by X3D vs. plain 9950X.
- pixl97 7mo agoIt really comes down to how much more this CPU is over the next one down if you're building a new rid for a long period of time. I'm running on a 5950X which is coming up on it's 6 years in November. I could have spend a little less on the next model down, but I expect this rig will last me for a few more years (especially with how much memory is). The per year extra expense for that CPU was almost nothing over its lifetime. Now, would I upgrade an existing computer with a slightly slower processor with it, probably not.
- sylware 7mo agoWith the best silicon tech, in R&D, what would be the maxium static RAM(L1 cache) you could really slap to a 8 core CPU? (Zero DRAM).
- pwr22 7mo agoI'm interested to know if the L3 cache all behaves as a single pool for any core on either CCD, whether there's a penalty in access time depending on locality or whether they are just entirely localised.
- undersuit 7mo agoAMD didn't have to introduce a special driver for the Ryzen 9 5950x to keep threads resident to the "gaming" CCD. There was only a small difference between the 5950x and the non-X3d Ryzen 7 5800x in workloads that didn't use more than 8 cores unlike the observed slowdowns in the Ryzen 9s 7950X3D and 7900X3D when they were released compared to the Ryzen 7 7800X3D . When the L3 sizes are different across CCDs the special AMD driver is needed to keep threads pinned to the larger L3 CCD and prevent them from being placed on the small L3 CCD where their memory requests can exploit the other CCD's L3 as an L4. The AMD driver reduces CCD to CCD data requests by keeping programs contained in one CCD. With equal L3 caches when a process spills onto the second CCD it will still use the first's L3 cache as "L4" but it no longer has to evict that data at the same rate as the lopsided models. Additionally the first CCD can use the second CCD's L3 in kind reducing the number of requests that need to go to main memory. The same sized L3s reduce contention to the IO die and the larger sized L3s reduce memory contention, it's a win-win. https://www.phoronix.com/review/amd-3d-vcache-optimizer-9950x3d/4 https://www.phoronix.com/review/amd-3d-vcache-optimizer-9950...
- phire 7mo agoThe short answer is that L3 is local to each CCD. And that answer is good enough for most workloads. You should stop reading now. _______________________ The complex answer is that there is some ability one CCD to pull cachelines from the other CCD. But I've never been able to find a solid answer for the limitations on this. I know it can pull a dirty cache line from the L1/L2 of another CCDs (this is the core-to-core latency test you often see in benchmarks, and there is an obvious cross-die latency hit). But I'm not sure it can pull a clean cacheline from another CCD at all, or if those just get redirected to main memory (as the latency to main memory isn't that much higher than between CCDs). And even if it can pull a clean cacheline, I'm not sure it can pull them from another CCD's L3 (which is an eviction cache, so only holds clean cachelines). The only way for a cacheline to get into a CCD's L3 is to be evicted from an L2 on that core, so if a dataset is active across both CCDs, it will end up duplicated across both L3s. Cachelines evicted from one L3 do NOT end up in another L3, so an idle CCD can't act as a pseudo L4. I haven't seen anyone make a benchmark which would show the effect, if it exists.
- swarnie 7mo agoFactorio mega basing just found a new ceiling.
- Lightkey 7mo agoI'm curious to see if that is true. The maximum amount of cache addressable per core didn't increase after all.
- senfiaj 7mo agoBack in 2004 my PC RAM was 256. My relative's laptop had 128. That's crazy when a modern CPU cache can theoretically host an OS (or even multiple OSes) from early 2000s.
- addaon 7mo agoThe Power4 MCM had 128 MB cache in 2001. The G4 TiBook sold the same year came with 128 MB of system RAM base, and OS X supported 64 MB configurations for a few years after this.
- egeozcan 7mo agoThe RAM prices are so high and the storage is also getting more expensive every day, so we're forced to fit everything inside the CPU cache as a solution! /s
- sqquima 7mo agoIt would be interesting if it allowed to use the cache as ram and could boot without any sticks on the motherboard.
- 0-_-0 7mo agoInstead of a cache you could put down an SRAM buffer, it would be more efficient than a cache and just as fast. And addressable. Interesting idea.
- addaon 7mo agoSeveral processors support this by effectively locking cache lines. At the low end, it allows a handful of fast interrupt routines without dedicated TCM. At the high end, it allows boot ROMs to negotiate DRAM links in software, avoiding both the catch 22 and complex hardware negotiation.
- rasz 7mo ago256MB was pretty much bare minimum to run contemporary software on a PC in 2004. "Feb 2001 128MB DIMM was $59. Aug 2001 256MB module was $49. Feb 2002 256MB $34. April 2003 hit bottom with $39 512MB DIMMs"
- jeremie_strand 7mo ago[dead]
- jeremie_strand 7mo ago[dead]
- rietta 7mo agoI am so grateful that I bought my 128 GB ram kit in January of last year for my own 9950 upgrade. We just built my dad a 7000 series to replace his old AM4 (2017 build) and 32 gigs DDR five was nearly the same price at Micro Center that I paid last year. I was able to gift him an Nvidia 1060 discreet graphics card so that he could continue to run his two monitors. The newer motherboards have much less on board capability for that.
- hu3 7mo ago1060 is a sweet card for multi monitor. good on you for gifting him.
- rietta 7mo agoI upgraded to a 4070 super last year. I ran both cards at the same time for a little bit, but it got really frustrating to keep the wrong card from being assigned to a particular task with llama. I really should’ve taken an R&D tax credit on my AI research but I’m still able to expense it for the business.
- Jotalea 7mo agoso you're telling me I can (theoretically) have a full Alpine Linux installation in just the CPU? I'm impressed
- varispeed 7mo agoI know the prices of RAM are high, but 256GB RAM limit seems like omission. If they supported at least 512GB in quad or eight channel that would be something worth looking at for me. I know there is Threadripper but ECC memory is out of reach.
- electronsoup 7mo agoWhenever I see a chip like this, I think "why wont my company let me use a decent computer"
- SubiculumCode 7mo agoOh man. I am running computations on my server that involve computing geodesic distances with the heat method. The job turns out to be a L3 cache thrasher, leaving my cpus underutilized for multi worker jobs .... 208mb instead of my 25 per socket sounds amazing
- AnthonyMouse 7mo agoThey sell essentially the same chips with more CCDs as Epyc instead of Ryzen. 9684X has more than 1GB of L3 per socket (but it's not cheap).
- MaximilianEmel 7mo agoThey should allow it to function without any external RAM.
- kristianp 7mo agoNobody adds L1+L2+L3 like that, because L1 stores a subset of L2 and L2 stores a subset of L3. Just say 192MB of L3.
- Retr0id 7mo agoIt depends on the implementation, it is possible for a cache line to be in L1 but not L2, etc.
- abcde666777 7mo agoA year ago I swapped out a 5800x for a 5800x3d to get more stable frame rates in Counterstrike 2. Made a sizable difference, especially to 1% lows, so these large caches can clearly be a big boon. Granted it's also obvious the game is poorly optimized, the gains look less significant for most other titles.