5 ms·

Easy RISC-V

401 points by todsacerdoti 1y ago

simonebrunozzi 1y ago
Great guide! I think the first "My first RISC-V assembly program" emulator plane should be right at the beginning of the guide. Otherwise, casual readers might think that this is a text-only introduction (despite the word "interactive" in the title). Will spend more time on it in the coming days. I am quite interested in RISC-V and I think that it might have a bright future ahead. If any AI expert is reading this now, please use Replit or Lovable or something like that to re-create "Core War" [0] with RISC-V assembly. It would be GREAT. [0]: https://en.wikipedia.org/wiki/Core_War https://en.wikipedia.org/wiki/Core_War
- antiphase 1y ago
  Why wouldn't someone just do this with their brain?
  - timeinput 1y ago
    I'm still busy building my ox-bike wagon. Soon I'll start pedaling around the country offering tea, and hand written (my brain to my keyboard ™) software.
  - crabmusket 1y ago
    I was going to add to your comment with some snarky rejoinder like "brain, is that a new agent from OpenAI?" or "we are all vibecoders now" or simply "ain't nobody got time for that". But then I got to wondering about the OP's statement that they would specifically like someone to create this with AI. It strikes me both as silly as saying "if you're good at using Visual Studio, could you do this?", because AI tools are just tools now, and those who want to use them don't need to be prompted... but also somehow fundamentally different. OP, what was on your heart that caused you to phrase it that way?
    - cloudhead 1y ago
      I think it's phrased that way because he's saying it would be great to have as long as you don't spend too much time on it. Doing it by hand would probably not be worth it, but if a tool can do it, then it's worth it.
aarroyoc 1y ago
Having learned assembly with the book "Computer Organization And Design" from Patterson and Hennessy, it really shows how much RISC-V takes from MIPS. After all they share some of the people involved in both ISAs and they have learned from the MIPS mistakes (no delay slots!). Basically if you come from a MIPS the assembly is very very similar, as it was my case. Now that book is also available with a RISC-V edition, which has a very interesting chapter comparing all different RISC ISAs and what they do differently (SH, Alpha, SPARC, PA-RISC, POWER, ARM, ...),... However I've been exploring AArch64 for some time and I think it has some very interesting ideas too. Maybe not as clean as RISC-V but with very pragmatic design and some choices that make me question if RISC-V was too conservative in its design.
- tonetegeatinst 1y ago
  Do you have a link to the risc-v version? I have the MIPS version and want to pick up the risc-v version.
  - 6SixTy 1y ago
    https://www.amazon.com/Computer-Organization-Design-RISC-V-Architecture/dp/0128203315 https://www.amazon.com/Computer-Organization-Design-RISC-V-A...
- fidotron 1y ago
  > However I've been exploring AArch64 for some time and I think it has some very interesting ideas too. Maybe not as clean as RISC-V but with very pragmatic design and some choices that make me question if RISC-V was too conservative in its design. Not enough people reflect on this, or the fact that it's remarkably hazy where exactly AArch64 came from and what guided the design of it.
  - zozbot234 1y ago
    AArch64 came from AArch32. That's why it keeps things like condition codes, which are a big mistake for large out-of-order implementations. RISC-V sensibly avoid this by having condition-and-branch instructions instead. Otherwise, RISC-V is conservative because it tries to avoid possibly encumbered techniques. But other than that it's remarkably simple and elegant.
doublerabbit 1y ago
Within the basic "123" ASM demo, I get that x10 - Becomes 0x00000123 as we are taking the integer of x0 and applying 123 to end of it but why is the sp (x2) register at 0x40100000? What is that sp? Is it important? Why isn't that at 0x000000? Why isn't that explained? That's when I get lost.
- ajxs 1y ago
  'sp' is the 'stack pointer' register. There's an explanation of the stack later in the guide: https://dramforever.github.io/easyriscv/#the-stack https://dramforever.github.io/easyriscv/#the-stack
cbm-vic-20 1y ago
I think there's an error in the Position Independence section: start: auipc a0, 3 addi a0, a0, 4 The text says that this should result in 0x3004; was this example intended to be start: lui a0, 3 addi a0, a0, 4
- brucehoult 1y ago
  No, because `lui` results in an absolute address, not a position independent one. The `auipc/addi` sequence results in 0x3004 + whatever the address of the `auipc` instruction itself is. If the `auipc` is at address 0 then the result will be the same.
  - jecel 1y ago
    Exactly, but the text has the same instruction sequence twice and the parent correctly indicated that the first copy should have used "lui" to illustrate the problem you mentioned and the second copy does use "auipc" to illustrate the fix you mentioned.
    - brucehoult 1y ago
      Oh, fair enough.
- brucehoult 1y ago
  This copypasta has been fixed.
deleted 1y ago
[deleted]
ordu 1y ago
> Subtracting from zero is negation. What’s the negative of 0x123? It is 0xfffffedd. > Hmm, we get 0xfffffccd. No, we didn't. The emulator shows 0xfffffedd, and I've checked it manually. The emulator is right.
triilman 1y ago
https://github.com/triilman25/tcp-socket-in-riscv-assembly https://github.com/triilman25/tcp-socket-in-riscv-assembly I wrote TCP Socket for RISCV by using ISA RV64I. You have to know about linker relaxation and how to using it. Some of reference I have attached there
liqilin1567 1y ago
I have to praise the interactive style of this content. As a C/C++ dev, I've always thought assembly was much harder. But this interactive content makes assembly clearer.
- IshKebab 1y ago
  RISC-V assembly is mostly very easy (but still super tedious). The main difficulty is their insistence on unnecessarily abbreviated instruction mnemonics. `lw` instead of `load4`, `j` instead of `jump`, and so on. I don't really understand why. We aren't writing these on punch cards.
Ethan312 1y ago
Nice project. RISC-V tools like this make learning architecture concepts much easier. It’s great to see more hands-on resources that help people move from theory to actual CPU behavior.
lachlanj 1y ago
Has anyone seen anything similar to this for x86?
- adgjlsfhk1 1y ago
  making this in x86 would be fairly tricky since there isn't the same sort of unified core (there used to be, but that was the 16 bit extension set which isn't how x86 is used now).
sshine 1y ago
The gods have spoken. I have reached “intro to assembly” in my C course this week and had decided on RISC-V to bridge the gap that everyone has different CPUs and that x86-64 is a little harder to learn than MIPS32, but MIPS32 isn’t as relevant. And here’s someone who made my course material for the subject entirely. Thank you so much.
crabmusket 1y ago
This really makes me want to try fiddling with some low-level stuff again. I studied mechatronics at uni and programmed microcontrollers in C and assembly, but have gone the webdev direction since then. Does anyone have any trusted quality resources for getting into RISC-V hardware? I'm especially interested in using Rust for this if possible - I've wanted an excuse to learn it in more depth for a while.
- 334f905d22bc19 1y ago
  Since Rust is not directly hardware, here is a nice tutorial on some simple OS basics: https://operating-system-in-1000-lines.vercel.app/en/ https://operating-system-in-1000-lines.vercel.app/en/ There was also some Rust specific OS tutorial somewhere that was written nicely, but I can't find it right now. Also if you want to get real hardware, there is the neorv32 that has nice documentation: https://stnolting.github.io/neorv32/ https://stnolting.github.io/neorv32/ https://github.com/stnolting/neorv32 https://github.com/stnolting/neorv32 It's a risc-v core written in VHDL
  - Gazoche 1y ago
    The Rust OS tutorial you're thinking of is probably this one: https://os.phil-opp.com/ https://os.phil-opp.com/
    - crabmusket 1y ago
      Thank you both! These are some really interesting places to pick up from.
- utopiah 1y ago
  > getting into RISC-V hardware? Got myself a https://docs.banana-pi.org/en/BPI-F3/BananaPi_BPI-F3 https://docs.banana-pi.org/en/BPI-F3/BananaPi_BPI-F3 in May last year for 90€. Tinkered again few weeks ago https://bsky.app/profile/benetou.fr/post/3m2m62st3hk2w https://bsky.app/profile/benetou.fr/post/3m2m62st3hk2w > I'm especially interested in using Rust for this if possible I didn't tinker with Rust on it but if I had to I'd probably try via https://github.com/dockcross/dockcross/tree/master/linux-riscv64 https://github.com/dockcross/dockcross/tree/master/linux-ris... and avoid compiling on the device itself, unless it's basically a HelloWorld project.
bigprovolone 1y ago
if you're looking for an nice RISCV emulator try RARS https://github.com/TheThirdOne/rars https://github.com/TheThirdOne/rars
ReFruity 1y ago
I like this. Do you have a link to your simulator code? I might borrow for a personal project of mine if it's ok.
- klelatti 1y ago
  https://github.com/dramforever/easyriscv/blob/main/emulator.js https://github.com/dramforever/easyriscv/blob/main/emulator....
Peteragain 1y ago
RISK-V - you can easily get the hardware: https://www.raspberrypi.com/news/risc-v-on-raspberry-pi-pico-2/ https://www.raspberrypi.com/news/risc-v-on-raspberry-pi-pico...
- abeindoria 1y ago
  It'd probably be easier to get on an ESP-32, no? Those are arguably more widely available.
- 334f905d22bc19 1y ago
  There will also be the visionfive 2 lite in (hopefully) a moment for more risc-v capabilities. I am excited about it. Haven't looked too much into it, but what I've heard is that the visionfive 2 is not too bad. Lacks a few drivers or performance in them. Will see. I am also curious how easy it can be used for some OS dev. https://www.kickstarter.com/projects/starfive/visionfive-2-lite-unlock-risc-v-sbc-at-199 https://www.kickstarter.com/projects/starfive/visionfive-2-l... And if someone wants to get fancy and do some HW-SW-Codesign with risc-v and FPGAs, then there is the PolarFireSoC. A lot cheaper than AMD/Xilinx products and okay-ish to use. Their dev enviroment feels kinda outdated, but at least it's snappy. Also the documentation feels kinda sparse, but most stuff is documented __somewhere__ - you just gotta find it. https://www.microchip.com/en-us/development-tool/MPFS-DISCO-KIT https://www.microchip.com/en-us/development-tool/MPFS-DISCO-... Fun fact: The dev board costs less than the chip itself. (Apparently that's often the case, but I just noticed that the first time)
  - brucehoult 1y ago
    There is more than one dev board. The Microchip "Icicle" came out in late 2020 with the largest FPGA in the range, made using pre-production chips. It was several years more before you could buy the chips themselves. Digikey says it's no longer manufactured and they're just running down stocks. The BeagleV "Fire" is much cheaper ($150) and uses one of the smallest FPGA parts in the range. GOWIN also has RISC-V FPGA SoCs (Arora V GW5AST series)
LarsDu88 1y ago
Great work! I was wondering about this after trying out Easy6502. It would be nice to have a more visual component like Easy6502 which has a draw buffer and snake game tho :)
- brucehoult 1y ago
  That's one of the first things I suggested to the author ... RV32I has a lot more registers to display than 6502, so I guess there was no room for the graphics output display. Maybe doing RV32E plus a graphics output would be a good compromise. Sixteen registers is probably enough for any program people are likely to write in this --- and you can tell GCC/LLVM to generate for RV32E if you want to compile C code and paste the asm in. (I'm not sure whether the assembler can actually cope with that)
sylware 1y ago
Even if there are not that expensive to implement, I do not use official ABI register names, neither pseudo-instructions (I use a command to generate the code on the side). Once RISC-V has performant silicon implementations (server/desktop/mobile/embedded), the really hard part will be to move the software stack, mostly closed source applications like video games. And a very big warning: do NOT abuse an assembler macro-preprocessor or you will lock your code on that very assembler. On my side I have been using a simple C pre-processor to keep the door open for any other assembler, at minimal technical cost.
- dontlaugh 1y ago
  The games are barely moving to ARM, they won’t move to yet another architecture. Desktop games will remain x86 windows for the foreseeable future merely due to the existing catalogue. The only exception is console games, where the architecture doesn’t matter anyway.
  - sylware 1y ago
    Yep, the super hard part: this rv64 "catalog" is empty. If you put emulation (hardware accelerated or not), game devs won't compile for rv64. Look at how valve proton is hurting native elf/linux gaming: game devs hardly build anymore for native elf/linux (but this may be related to the toxic behavior of some glibc and gcc devs though), even though their game engine has everything linux support.
    - Firehawke 1y ago
      It's also how easy the userland can break things. Windows backwards compatibility tends (even if it's not 100% successful on this) to stay relatively stable. It's kind of funny that the most compatible way to distribute Linux binaries for games is to target Proton/Wine.
      - sylware 1y ago
        proton/wine has no official technical support hence illegal in tons of countries. Since proton/wine is unreliable in time, this is a disaster. And there is a lot of BS around that: if some devs support their game on elf/linux via proton, they will have to QA it on a linux system anyway, so it does not change that much, even less with a game engine which has everything linux already... it only add the ultra-heavy-complex and then bug inducing proton/wine layer... an horrible mess to debug. One unfortunate patch, proton/wine side or game side, and compat is gone, and you are toast... and those patches do happen. Conclusion: the only sane way is PROTON = 0 BUCKS. I play only F2P games with proton (mostly gachas), no way I'll pay bucks for a game without technical support. Valve should allow to pay games _only_ for the games with official elf/linux/proton support (aka the game devs do QA on elf/linux with valve proton... which would be no better than stupid if their game engine has elf/linux support already in). Why not let elf/linux users play all games which do not have official elf/linux support for free, well, those which run, and run decently, and until an unfortunate patch...
ks2048 1y ago
This looks great. I like how it starts with a dump of all the instructions we'll be using. Does anyone know of a complete list, machine readable? e.g. instructions = [{"name": "lui", "description": "load upper immediate", "args": [...]}, ...]
ge96 1y ago
tangent I want to link back to this https://github.com/mortbopet/Ripes https://github.com/mortbopet/Ripes

401 points by todsacerdoti 1y ago

Great guide! I think the first "My first RISC-V assembly program" emulator plane should be right at the beginning of the guide. Otherwise, casual readers might think that this is a text-only introduction (despite the word "interactive" in the title). Will spend more time on it in the coming days. I am quite interested in RISC-V and I think that it might have a bright future ahead. If any AI expert is reading this now, please use Replit or Lovable or something like that to re-create "Core War" [0] with RISC-V assembly. It would be GREAT. [0]: https://en.wikipedia.org/wiki/Core_War https://en.wikipedia.org/wiki/Core_War

antiphase 1y ago
Why wouldn't someone just do this with their brain?
- timeinput 1y ago
  I'm still busy building my ox-bike wagon. Soon I'll start pedaling around the country offering tea, and hand written (my brain to my keyboard ™) software.
- crabmusket 1y ago
  I was going to add to your comment with some snarky rejoinder like "brain, is that a new agent from OpenAI?" or "we are all vibecoders now" or simply "ain't nobody got time for that". But then I got to wondering about the OP's statement that they would specifically like someone to create this with AI. It strikes me both as silly as saying "if you're good at using Visual Studio, could you do this?", because AI tools are just tools now, and those who want to use them don't need to be prompted... but also somehow fundamentally different. OP, what was on your heart that caused you to phrase it that way?
  - cloudhead 1y ago
    I think it's phrased that way because he's saying it would be great to have as long as you don't spend too much time on it. Doing it by hand would probably not be worth it, but if a tool can do it, then it's worth it.

aarroyoc 1y ago

Having learned assembly with the book "Computer Organization And Design" from Patterson and Hennessy, it really shows how much RISC-V takes from MIPS. After all they share some of the people involved in both ISAs and they have learned from the MIPS mistakes (no delay slots!). Basically if you come from a MIPS the assembly is very very similar, as it was my case. Now that book is also available with a RISC-V edition, which has a very interesting chapter comparing all different RISC ISAs and what they do differently (SH, Alpha, SPARC, PA-RISC, POWER, ARM, ...),... However I've been exploring AArch64 for some time and I think it has some very interesting ideas too. Maybe not as clean as RISC-V but with very pragmatic design and some choices that make me question if RISC-V was too conservative in its design.

tonetegeatinst 1y ago
Do you have a link to the risc-v version? I have the MIPS version and want to pick up the risc-v version.
- 6SixTy 1y ago
  https://www.amazon.com/Computer-Organization-Design-RISC-V-Architecture/dp/0128203315 https://www.amazon.com/Computer-Organization-Design-RISC-V-A...
fidotron 1y ago
> However I've been exploring AArch64 for some time and I think it has some very interesting ideas too. Maybe not as clean as RISC-V but with very pragmatic design and some choices that make me question if RISC-V was too conservative in its design. Not enough people reflect on this, or the fact that it's remarkably hazy where exactly AArch64 came from and what guided the design of it.
- zozbot234 1y ago
  AArch64 came from AArch32. That's why it keeps things like condition codes, which are a big mistake for large out-of-order implementations. RISC-V sensibly avoid this by having condition-and-branch instructions instead. Otherwise, RISC-V is conservative because it tries to avoid possibly encumbered techniques. But other than that it's remarkably simple and elegant.

doublerabbit 1y ago

Within the basic "123" ASM demo, I get that x10 - Becomes 0x00000123 as we are taking the integer of x0 and applying 123 to end of it but why is the sp (x2) register at 0x40100000? What is that sp? Is it important? Why isn't that at 0x000000? Why isn't that explained? That's when I get lost.

ajxs 1y ago
'sp' is the 'stack pointer' register. There's an explanation of the stack later in the guide: https://dramforever.github.io/easyriscv/#the-stack https://dramforever.github.io/easyriscv/#the-stack

cbm-vic-20 1y ago

I think there's an error in the Position Independence section: start: auipc a0, 3 addi a0, a0, 4 The text says that this should result in 0x3004; was this example intended to be start: lui a0, 3 addi a0, a0, 4

brucehoult 1y ago
No, because `lui` results in an absolute address, not a position independent one. The `auipc/addi` sequence results in 0x3004 + whatever the address of the `auipc` instruction itself is. If the `auipc` is at address 0 then the result will be the same.
- jecel 1y ago
  Exactly, but the text has the same instruction sequence twice and the parent correctly indicated that the first copy should have used "lui" to illustrate the problem you mentioned and the second copy does use "auipc" to illustrate the fix you mentioned.
  - brucehoult 1y ago
    Oh, fair enough.
brucehoult 1y ago
This copypasta has been fixed.

deleted 1y ago

[deleted]

ordu 1y ago

> Subtracting from zero is negation. What’s the negative of 0x123? It is 0xfffffedd. > Hmm, we get 0xfffffccd. No, we didn't. The emulator shows 0xfffffedd, and I've checked it manually. The emulator is right.

triilman 1y ago

https://github.com/triilman25/tcp-socket-in-riscv-assembly https://github.com/triilman25/tcp-socket-in-riscv-assembly I wrote TCP Socket for RISCV by using ISA RV64I. You have to know about linker relaxation and how to using it. Some of reference I have attached there

liqilin1567 1y ago

I have to praise the interactive style of this content. As a C/C++ dev, I've always thought assembly was much harder. But this interactive content makes assembly clearer.

IshKebab 1y ago
RISC-V assembly is mostly very easy (but still super tedious). The main difficulty is their insistence on unnecessarily abbreviated instruction mnemonics. `lw` instead of `load4`, `j` instead of `jump`, and so on. I don't really understand why. We aren't writing these on punch cards.

Ethan312 1y ago

Nice project. RISC-V tools like this make learning architecture concepts much easier. It’s great to see more hands-on resources that help people move from theory to actual CPU behavior.

lachlanj 1y ago

Has anyone seen anything similar to this for x86?

adgjlsfhk1 1y ago
making this in x86 would be fairly tricky since there isn't the same sort of unified core (there used to be, but that was the 16 bit extension set which isn't how x86 is used now).

sshine 1y ago

The gods have spoken. I have reached “intro to assembly” in my C course this week and had decided on RISC-V to bridge the gap that everyone has different CPUs and that x86-64 is a little harder to learn than MIPS32, but MIPS32 isn’t as relevant. And here’s someone who made my course material for the subject entirely. Thank you so much.

crabmusket 1y ago

This really makes me want to try fiddling with some low-level stuff again. I studied mechatronics at uni and programmed microcontrollers in C and assembly, but have gone the webdev direction since then. Does anyone have any trusted quality resources for getting into RISC-V hardware? I'm especially interested in using Rust for this if possible - I've wanted an excuse to learn it in more depth for a while.

334f905d22bc19 1y ago
Since Rust is not directly hardware, here is a nice tutorial on some simple OS basics: https://operating-system-in-1000-lines.vercel.app/en/ https://operating-system-in-1000-lines.vercel.app/en/ There was also some Rust specific OS tutorial somewhere that was written nicely, but I can't find it right now. Also if you want to get real hardware, there is the neorv32 that has nice documentation: https://stnolting.github.io/neorv32/ https://stnolting.github.io/neorv32/ https://github.com/stnolting/neorv32 https://github.com/stnolting/neorv32 It's a risc-v core written in VHDL
- Gazoche 1y ago
  The Rust OS tutorial you're thinking of is probably this one: https://os.phil-opp.com/ https://os.phil-opp.com/
  - crabmusket 1y ago
    Thank you both! These are some really interesting places to pick up from.
utopiah 1y ago
> getting into RISC-V hardware? Got myself a https://docs.banana-pi.org/en/BPI-F3/BananaPi_BPI-F3 https://docs.banana-pi.org/en/BPI-F3/BananaPi_BPI-F3 in May last year for 90€. Tinkered again few weeks ago https://bsky.app/profile/benetou.fr/post/3m2m62st3hk2w https://bsky.app/profile/benetou.fr/post/3m2m62st3hk2w > I'm especially interested in using Rust for this if possible I didn't tinker with Rust on it but if I had to I'd probably try via https://github.com/dockcross/dockcross/tree/master/linux-riscv64 https://github.com/dockcross/dockcross/tree/master/linux-ris... and avoid compiling on the device itself, unless it's basically a HelloWorld project.

bigprovolone 1y ago

if you're looking for an nice RISCV emulator try RARS https://github.com/TheThirdOne/rars https://github.com/TheThirdOne/rars

ReFruity 1y ago

I like this. Do you have a link to your simulator code? I might borrow for a personal project of mine if it's ok.

klelatti 1y ago
https://github.com/dramforever/easyriscv/blob/main/emulator.js https://github.com/dramforever/easyriscv/blob/main/emulator....

Peteragain 1y ago

RISK-V - you can easily get the hardware: https://www.raspberrypi.com/news/risc-v-on-raspberry-pi-pico-2/ https://www.raspberrypi.com/news/risc-v-on-raspberry-pi-pico...

abeindoria 1y ago
It'd probably be easier to get on an ESP-32, no? Those are arguably more widely available.
334f905d22bc19 1y ago
There will also be the visionfive 2 lite in (hopefully) a moment for more risc-v capabilities. I am excited about it. Haven't looked too much into it, but what I've heard is that the visionfive 2 is not too bad. Lacks a few drivers or performance in them. Will see. I am also curious how easy it can be used for some OS dev. https://www.kickstarter.com/projects/starfive/visionfive-2-lite-unlock-risc-v-sbc-at-199 https://www.kickstarter.com/projects/starfive/visionfive-2-l... And if someone wants to get fancy and do some HW-SW-Codesign with risc-v and FPGAs, then there is the PolarFireSoC. A lot cheaper than AMD/Xilinx products and okay-ish to use. Their dev enviroment feels kinda outdated, but at least it's snappy. Also the documentation feels kinda sparse, but most stuff is documented __somewhere__ - you just gotta find it. https://www.microchip.com/en-us/development-tool/MPFS-DISCO-KIT https://www.microchip.com/en-us/development-tool/MPFS-DISCO-... Fun fact: The dev board costs less than the chip itself. (Apparently that's often the case, but I just noticed that the first time)
- brucehoult 1y ago
  There is more than one dev board. The Microchip "Icicle" came out in late 2020 with the largest FPGA in the range, made using pre-production chips. It was several years more before you could buy the chips themselves. Digikey says it's no longer manufactured and they're just running down stocks. The BeagleV "Fire" is much cheaper ($150) and uses one of the smallest FPGA parts in the range. GOWIN also has RISC-V FPGA SoCs (Arora V GW5AST series)

LarsDu88 1y ago

Great work! I was wondering about this after trying out Easy6502. It would be nice to have a more visual component like Easy6502 which has a draw buffer and snake game tho :)

brucehoult 1y ago
That's one of the first things I suggested to the author ... RV32I has a lot more registers to display than 6502, so I guess there was no room for the graphics output display. Maybe doing RV32E plus a graphics output would be a good compromise. Sixteen registers is probably enough for any program people are likely to write in this --- and you can tell GCC/LLVM to generate for RV32E if you want to compile C code and paste the asm in. (I'm not sure whether the assembler can actually cope with that)

sylware 1y ago

Even if there are not that expensive to implement, I do not use official ABI register names, neither pseudo-instructions (I use a command to generate the code on the side). Once RISC-V has performant silicon implementations (server/desktop/mobile/embedded), the really hard part will be to move the software stack, mostly closed source applications like video games. And a very big warning: do NOT abuse an assembler macro-preprocessor or you will lock your code on that very assembler. On my side I have been using a simple C pre-processor to keep the door open for any other assembler, at minimal technical cost.

dontlaugh 1y ago
The games are barely moving to ARM, they won’t move to yet another architecture. Desktop games will remain x86 windows for the foreseeable future merely due to the existing catalogue. The only exception is console games, where the architecture doesn’t matter anyway.
- sylware 1y ago
  Yep, the super hard part: this rv64 "catalog" is empty. If you put emulation (hardware accelerated or not), game devs won't compile for rv64. Look at how valve proton is hurting native elf/linux gaming: game devs hardly build anymore for native elf/linux (but this may be related to the toxic behavior of some glibc and gcc devs though), even though their game engine has everything linux support.
  - Firehawke 1y ago
    It's also how easy the userland can break things. Windows backwards compatibility tends (even if it's not 100% successful on this) to stay relatively stable. It's kind of funny that the most compatible way to distribute Linux binaries for games is to target Proton/Wine.
    - sylware 1y ago
      proton/wine has no official technical support hence illegal in tons of countries. Since proton/wine is unreliable in time, this is a disaster. And there is a lot of BS around that: if some devs support their game on elf/linux via proton, they will have to QA it on a linux system anyway, so it does not change that much, even less with a game engine which has everything linux already... it only add the ultra-heavy-complex and then bug inducing proton/wine layer... an horrible mess to debug. One unfortunate patch, proton/wine side or game side, and compat is gone, and you are toast... and those patches do happen. Conclusion: the only sane way is PROTON = 0 BUCKS. I play only F2P games with proton (mostly gachas), no way I'll pay bucks for a game without technical support. Valve should allow to pay games _only_ for the games with official elf/linux/proton support (aka the game devs do QA on elf/linux with valve proton... which would be no better than stupid if their game engine has elf/linux support already in). Why not let elf/linux users play all games which do not have official elf/linux support for free, well, those which run, and run decently, and until an unfortunate patch...

ks2048 1y ago

This looks great. I like how it starts with a dump of all the instructions we'll be using. Does anyone know of a complete list, machine readable? e.g. instructions = [{"name": "lui", "description": "load upper immediate", "args": [...]}, ...]

ge96 1y ago

tangent I want to link back to this https://github.com/mortbopet/Ripes https://github.com/mortbopet/Ripes