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Mysterious Intrigue Around an x86 "Corporate Entity Other Than Intel/AMD"
- IlikeKitties 1y ago> Mysterious https://en.wikipedia.org/wiki/Zhaoxin https://en.wikipedia.org/wiki/Zhaoxin
- Qem 1y agoThere are others too. See https://en.wikipedia.org/wiki/List_of_x86_manufacturers https://en.wikipedia.org/wiki/List_of_x86_manufacturers
- senkora 1y agoSpecifically, the AMD-Chinese joint venture seems like one of the more probable choices: https://en.wikipedia.org/wiki/AMD%E2%80%93Chinese_joint_venture https://en.wikipedia.org/wiki/AMD%E2%80%93Chinese_joint_vent...
- tssva 1y agoZhaoxin is addressed in the article and also why the author considers it unlikely they are the "corporate entity" in question.
- ok123456 1y agoEither Chinese or Russian x86 clones. Diplomatically not named.
- anticodon 1y agoThere's only Russian (Soviet) clone of 8086. There was some finished work on cloning 286 but they were never produced in series, since USSR collapsed.
- Tevo 1y agoDidn't one of the Elbrus CPUs have an x86 translation layer in hardware? Trying to get that to execute code at reasonable speeds, Transmeta style, to use as a replacement to western-supplied hardware wherever you have an explicit need for x86 wouldn't sound particularly far-fetched to me, if I didn't know so little about what's going on within Russia.
- anticodon 1y agoIt seems there's only software emulation of x86 on Elbrus.
- deleted 1y ago[deleted]
- mikece 1y agoDid Cyrix cease to exist or is this someone using their x86 license? EDIT: That's exactly what it is! They are a joint venture with VIA which acquired most of Cyrix in 1999: https://en.wikipedia.org/wiki/VIA_Technologies https://en.wikipedia.org/wiki/VIA_Technologies
- JonathonW 1y agoAnd Cyrix MediaGX (which remained with National Semiconductor after the VIA acquisition) became Geode which was eventually sold to AMD.
- diamond559 1y agoVIA has their own license and joint CPU project w/ a Chinese company apparently, could be related to that?
- aleph_minus_one 1y ago> They are a joint venture with VIA which acquired most of Cyrix in 1999 FYI: Zhaoxin (兆芯) [1] is a Joint Venture between VIA Technologies (威盛電子) and the Shanghai Municipal Government. Zhaoxin is mentioned in the article: "As pointed out in the Phoronix Forums, it could be Zhaoxin. But as they have contributed GCC patches, Glibc patches, Linux kernel patches, etc, over the years it's not clear why they would go unnamed or have to relay the message via Ludloff rather than their prior direct mailing list posts." [1] https://en.wikipedia.org/wiki/Zhaoxin https://en.wikipedia.org/wiki/Zhaoxin
- steve1977 1y agoCyrix… that's a name I've not heard in a long time
- eigenform 1y agoI wonder if this is in response to FineIBT trying to figure out what to use as an undefined opcode? Apparently 0xd6 is being reserved as undefined going forward: https://lore.kernel.org/lkml/20250814111732.GW4067720@noisy.programming.kicks-ass.net/ https://lore.kernel.org/lkml/20250814111732.GW4067720@noisy....
- dzdt 1y agoBy what legal mechanism is it restricted that not any random company can make their own independent implementation of hardware that interoperates with x86 software?
- mschuster91 1y agoThere are independent implementations of x86 at least in software - QEMU can do full emulation at the cost of it being dog slow, which is about the only choice for running fully x86 virtual machines on ARM - no aid from Rosetta for anything. The problem is the hardware magics you need to make x86 actually performant, there's a lot of patents surrounding that area.
- fluoridation 1y ago>The problem is the hardware magics you need to make x86 actually performant, there's a lot of patents surrounding that area. Those aren't even patented, they're straight up trade secrets. The relevant IPs concern the ISAs alone. Without doing anything too crazy you could implement x86 on your own silicon and make something that's slower than mainstream processors, but still usable for some things; certainly better than emulation in software, that's for sure.
- jacquesm 1y agoDo you have an example of such a project? I'd love to do this on an FPGA.
- phendrenad2 1y agohttps://github.com/MiSTer-devel/ao486_MiSTer https://github.com/MiSTer-devel/ao486_MiSTer Google is your freeeend
- jacquesm 1y agoNot quite. That's a board that contains both an FPGA and an ARM, what I meant was a board that just uses the FPGA for everything and an i386 or better core without any auxiliary processors. 100% clean hardware. But thank you for the link, fascinating project.
- sehugg 1y agoYou mean in 2025 someone is getting paid in their job to mess with x86 segment registers? I'd do that stuff for free.
- eqvinox 1y agoThey're just using the encoding for PUSH CS, presumably the actual instruction doesn't concern segment registers… I hope…
- deleted 1y ago[deleted]
- Teknoman117 1y agoThere's also this fun company (DM&P): https://www.vortex86.com https://www.vortex86.com Their "Vortex86DX3" is basically a dual-core 1 GHz Pentium II system on a chip...
- tyfighter 1y agoThis is something I heard through the grape vine years ago, but when you're a very large corporation negotiating CPU purchasing contracts in quantities of millions, you can get customizations that aren't possible outside of gigantic data centers. Things like enabling custom microcode (and development support) for adding new instructions for the benefit of your custom JIT-ed server infrastructure. The corporate entity here is likely a hyperscaler that everyone knows.
- jeffbee 1y agoSome of the public x86 ISA extensions were things that hyperscalers specifically requested.
- clausecker 1y agoSuch as?
- kijiki 1y agoMost of the Intel cache partitioning things were driven primarily by Google. The holy grail was to colocate latency-sensitive tasks with bulk background tasks to increase cluster utilization.
- jeffbee 1y agoI guess technically CAT and RDT are not ISA extensions because they are managed by MSRs. I was thinking of aspects of BMI, but I am sure that large-scale buyers had input into things like vector extensions, PMU features, and the things you mentioned as well.
- dboreham 1y agoHistorically the large buyer that could do this was NSA. Men in black would show up and tell you to add a bit population count instruction to your CPU..
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- eqvinox 1y agoThe block alignment of the text in the e-mail (https://sourceware.org/pipermail/binutils/2025-October/144875.html https://sourceware.org/pipermail/binutils/2025-October/14487...) is triggering some serious tilt for me…
- syncsynchalt 1y agoI wonder how long he worked on the "at this particular time" line before giving up?
- aleph_minus_one 1y agoMy attempt as a non-native English speaker: - CPUID range E000_xxxxh - unspecified leaf return values as of the day of 2025-10-14
- progval 1y agoIf you want more of this: https://www.youtube.com/watch?v=Y65FRxE7uMc https://www.youtube.com/watch?v=Y65FRxE7uMc . You can skip to 7:45 if the long intro bores you, but it's worth listening to it.
- NobodyNada 1y ago> I was asked to relay this to binutils/LKML. > As of 2025, the following are in active use by a corporate entity other than Intel/AMD. > Any collisions with them should be avoided. What's the purpose of sending this email to these mailing lists -- who cares about assigning x86 instruction opcodes other than Intel and AMD? Do Linux and binutils need to know about unused x86 opcodes in some way? And even if they did...why do unaffiliated open-source projects need to care about a nonstandard architecture extension from a company so secretive about it they won't even name themselves?
- nateb2022 1y agoLast month, Nvidia and Intel announced jointly developed 'Intel x86 RTX SOCs' + custom Nvidia data center x86 processors.[0] Opcodes 0Fh,3Ah,E0h...EFh combined with VEX/EVEX encoding suggests wide (256/512-bit) vector SIMD, possibly for matrix multiplication, tensor operations, or arbitrary neural network activation functions. [0]: https://nvidianews.nvidia.com/news/nvidia-and-intel-to-develop-ai-infrastructure-and-personal-computing-products https://nvidianews.nvidia.com/news/nvidia-and-intel-to-devel...
- snvzz 1y agoPossibly a legacy ISA acceleration feature in an upcoming RISC-V processor.