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Optimizing ClickHouse for Intel's ultra-high core count processors
- epistasis 1y agoThis is my favorite type of HN post, and definitely going to be a classic in the genre for me. > Memory optimization on ultra-high core count systems differs a lot from single-threaded memory management. Memory allocators themselves become contention points, memory bandwidth is divided across more cores, and allocation patterns that work fine on small systems can create cascading performance problems at scale. It is crucial to be mindful of how much memory is allocated and how memory is used. In bioinformatics, one of the most popular alignment algorithms is roughly bottlenecked on random RAM access (the FM-index on the BWT of the genome), so I always wonder how these algorithms are going to perform on these beasts. It's been a decade since I spent any time optimizing large system performance for it though. NUMA was already challenging enough! I wonder how many memory channels these new chips have access to.
- ashvardanian 1y agoMy expectation, they will perform great! I’m now mostly benchmarking on 192 core Intel, AMD, and Arm instances on AWS, and in some workloads they come surprisingly close to GPUs even on GPU-friendly workloads, once you get the SIMD and NUMA pinning parts right. For BioInformatics specifically, I’ve just finished benchmarking Intel SPR 16-core UMA slices against Nvidia H100, and will try to extend them soon: https://github.com/ashvardanian/StringWa.rs https://github.com/ashvardanian/StringWa.rs
- bob1029 1y agoThe most ideal arrangement is one in which you do not need to use the memory subsystem in the first place. If two threads need to communicate back-forth with each other in a very tight loop in order to get some kind of job done, there is almost certainly a much faster technique that could be ran on a single thread. Physically moving the information between the cores of processing is the most expensive part. You can totally saturate the memory bandwidth of a Zen chip with somewhere around 8-10 cores if they're all going at a shared working set really aggressively. Core-to-Core communication across infinity fabric is on the order of 50~100x slower than L1 access. Figuring out how to arrange your problem to meet this reality is the quickest path to success if you intend to leverage this kind of hardware. Recognizing that your problem is incompatible can also save you a lot of frustration. If your working sets must be massive monoliths and hierarchical in nature, it's unlikely you will be able to use a 256+ core monster part very effectively.
- jeffbee 1y agoNote that none of the CPUs in the article have that Zen architecture. One of the most interesting and poorly exploited features of these new Intel chips is that four cores share an L2 cache, so cooperation among 4 threads can have excellent efficiency. They also have user-mode address monitoring, which should be awesome for certain tricks, but unfortunately like so many other ISA extentions, it doesn't work. https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/monitor-umonitor-performance-guidance.html https://www.intel.com/content/www/us/en/developer/articles/t...
- Moto7451 1y agoOne of the use cases for Clickhouse and related columnar stores is simply to process all your data as quickly as possible where “all” is certainly more than what will fit in memory and in some cases more than what will fit on a single disk. For these I’d expect the allocator issue is contention when working with the MMU, TLB, or simply allocators that are not lock free (like the standard glibc allocator). Where possible one trick is to pre-allocate as much as possible for your worker pool so you get that out of the way and stop calling malloc once you begin processing. If you can swing it you replace chunks of processed data with new data within the same allocated area. At a previous job our custom search engine did just this to scale out better on the AWS X1 instances we were using for processing data.
- pixelpoet 1y agoThis post looks like excellent low-level optimisation writing just in the first sections, and (I know this is kinda petty, but...) my heart absolutely sings at their use of my preferred C++ coding convention where & (ref) neither belongs to the type nor the variable name!
- nivertech 1y agoI think it belongs to type, but since they use “auto” it looks standalone and can be confused with the “&” operator. I personally always used * and & as a prefix of the variable name, not as a suffix in the type name, except when used to specify types in templates.
- pixelpoet 1y agoIMO it's a separate category of modifiers/decorators to the type, like how adjectives and nouns are distinguished, and the only reason we have the false-choice in C/C++ is because it's not alphanumeric (if the token were e.g. "ref" it would interfere with the type or variable name in either other convention). If I were forced at gunpoint to choose one of the type or name, "obviously" I would also choose type.
- bee_rider 1y ago288 cores is an absurd number of cores. Do these things have AVX512? It looks like some of the Sierra Forest chips do have AVX512 with 2xFMA… That’s pretty wide. Wonder if they should put that thing on a card and sell it as a GPU (a totally original idea that has never been tried, sure…).
- singhrac 1y agoThe 288 core SKU (I believe 6900E) isn't very widely available, I think only to big clouds?
- sdairs 1y agohow long until I have 288 cores under my desk I wonder?
- zokier 1y agoDoes 2x160 cores count? https://www.titancomputers.com/Titan-A900-Octane-Dual-AMD-EPYC-Turin-9005-Serie-p/a900.htm https://www.titancomputers.com/Titan-A900-Octane-Dual-AMD-EP...
- deleted 1y ago[deleted]
- sbarre 1y agoDamn, when I first landed on the page I saw $7,600 and thought "for 320 cores that's pretty amazing!" but that's the default configuration with 32 cores & 64GB of memory. 320 cores starts at $28,000.. $34k with 1TB of memory..
- mrheosuper 1y agoThe CPU has launch price of $13k already, so $28k is a good deal imo
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- jiehong 1y agoGreat work! I like duckdb, but clickhouse seems more focused on large scale performance. I just thought that the article is written from the point of view of a single person, but has multiple authors, which is a bit weird. Did I misunderstood something?
- hobo_in_library 1y agoNot sure what happened here, but it's not uncommon for a post to have one primary author and then multiple reviewers/supporters also credited
- sdairs 1y agoYep that's pretty much the case here!
- sdairs 1y agoClickHouse works in-process and on the CLI just like DuckDB, but also scales to hundreds of nodes - so it's really not limited to just large scale. Handling those smaller cases with a great experience is still a big focus for us
- _jsmh 1y agoI'd like to see ClickHouse change its query engine to use Optimistic Concurrency Control.
- secondcoming 1y agoThose ClickHouse people get to work on some cool stuff
- sdairs 1y agoWe do! (and we're hiring!)
- vlovich123 1y agoI'm generally surprised they're still using the unmaintained old version of jemalloc instead of a newer allocator like the Bazel-based TCMalloc or mimalloc which have significantly better techniques due to better OS primitives & about a decade or so of R&D behind them.
- mrits 1y agobesides jemalloc also being used by other columnar databases it has a lot of control and telemetry built in. I don't closely follow tcmalloc but I'm not sure it focuses on large objects and fragmentation over months/years.
- jeffbee 1y agoTCMalloc has an absurd amount of bookkeeping and stats, but you have to understand the implementation deeply to make sense of the stats. https://github.com/google/tcmalloc/blob/master/docs/stats.md https://github.com/google/tcmalloc/blob/master/docs/stats.md
- drchaim 1y agoit seems they have tested it: https://github.com/ClickHouse/ClickHouse/issues/34157 https://github.com/ClickHouse/ClickHouse/issues/34157
- lordnacho 1y agoClickhouse is excellent btw. I took it for a spin, loading a few TB of orderbook changes into it as entire snapshots. The double compression (type-aware and generic) does wonders. It's amazing how you get both the benefit of small size and quick querying, with minimal tweaks. I don't think I changed any system level defaults, yet I can aggregate through the entire few billion snapshots in a few minutes.
- kookamamie 1y agoNUMA is satan. Source: Working in real-time computer vision.
- DeathArrow 1y ago>Intel's latest processor generations are pushing the number of cores in a server to unprecedented levels - from 128 P-cores per socket in Granite Rapids to 288 E-cores per socket in Sierra Forest, with future roadmaps targeting 200+ cores per socket. It seems today's Intel CPU can replace yesteryear's data center. May someone can try for fun running 1000 Red Hat Linux 6.2 in parallel on one CPU, like it's year 2000 again.
- adrian_b 1y agoDue to a typo, the title is confusing, at the first glance I thought that "Intel 280" might be some kind of Arrow Lake CPU (intermediate between Intel 275 and Intel 285), but the correct title should have said "Intel's 288-core processors", making clear that this is about the server CPUs with 288 E-cores, Sierra Forest and the future Clearwater Forest.
- scott_w 1y agoSame here. I don't know if the linked title changed but it's now: > Optimizing ClickHouse for Intel's ultra-high core count processors Which is pretty unambiguous.
- sdairs 1y agoYeah "Optimizing ClickHouse for Intel's ultra-high core count processors" is the original, unchanged article title, it's just been submitted slightly differently on HN (surprised mods haven't changed it here actually)
- tomhow 1y agoThanks, we've just changed the title to match the article's title, which the guidelines ask us to do.
- menaerus 1y agoTwo-character SIMD filtering improved performance significantly: ClickBench query Q20 sped up by 35% Other queries which perform substring matching saw an overall improvement of ~10% The geometric mean of all queries improved by 4.1% ClickBench dataset is ~70G IIRC so I find it interesting that they measured such a substantial speedup while only using SSE4.1 (128-bit) - so, not even AVX2 and much less AVX-512. I wonder what the results would be if latter had been the case. And I also wonder if this is (partly) an artifact of more laser-focused utilization of a CPU core ALU and memory subsystem. E.g. crunching more work into a single or pair of instructions are now leaving more space for other unrelated instructions to be retired.
- kwillets 1y agoThe SIMD string matching optimization unfortunately missed a trick -- it's more selective to match the first and last characters of a pattern than the first two, and it's the same cost. Credit to Muła for this one: http://0x80.pl/notesen/2016-11-28-simd-strfind.html#generic-sse-avx2 http://0x80.pl/notesen/2016-11-28-simd-strfind.html#generic-... .
- fuy 1y agoLooking at first optimization, I wonder if double-checking after acquiring exclusive lock brings any performance benefits. The whole premise is that cache access is read-heavy, so not acquiring exclusive locks for reads eliminates by far the biggest problem. Rare (I presume) cases of overlapping updates from different threads (considering updates themselves are also infrequent) don't seem like a big deal compared to lock elimination. Would be interesting to see benchmark numbers for those optimizations separately.