6 ms·
Most people do not realize how slow RISC-V is right now. Yes, it will definitely get better, but it will take some time given how far behind it is. Like 30x s
by bhouston 2y ago
Most people do not realize how slow RISC-V is right now. Yes, it will definitely get better, but it will take some time given how far behind it is.
Like 30x slower than a top of the line Apple Mx series CPU. Maybe there is a high performing RISC-V chip out there but I haven't yet run into one.
RISC-V benchmarks: https://browser.geekbench.com/search?q=RISC-V https://browser.geekbench.com/search?q=RISC-V. Compare to an Apple M4 benchmark: https://browser.geekbench.com/v6/cpu/8224953 https://browser.geekbench.com/v6/cpu/8224953
That said, RISC-V is good for embedded applications where raw performance isn't a factor. I think no other markets are yet accessible to RISC-V chips until their performance massively improves.
- tightbookkeeper 2y agoIs it slower by design or just because it’s implementations have not been aggressively optimized?
- bhouston 2y agoI believe it is just lacking aggressive optimization. ARM is basically RISC as well, so it isn't an architectural limitation.
- tightbookkeeper 2y ago(Naive question) then is it really a big hurdle for a company who knows how to make arm chips to try making riscv chips?
- bhouston 2y agoI suspect not? I think the principles and methods of optimization are the same. But I say this as a software guy who doesn't actually know CPU design.
- 1123581321 2y agoIt’s not a big hurdle so long as they hire Jim Keller to rapidly improve yet another architecture. (Only half-joking.)
- topspin 2y agoJim Keller is actually working on this right now at Tenstorrent.
- snvzz 2y agoAscalon (claiming Zen5-tier performance) is done, and has been available for licensing for about a year now. It was then made public that LG bought a license right away.
- saagarjha 2y agoIt’s easy to claim a lot of things.
- snvzz 2y ago>It’s easy to claim a lot of things. It certainly is easy to casually spread fear and doubt. But it is really far-fetched to think that the people at Tenstorrent, who have successfully delivered very high performance microarchitectures in other companies before, are lying about Ascalon, and that LG is helping them do that. It would even be more far fetched to claim that Ventana Veyron V2, SiFive P870, Akeana 5000-series, all of them available high performance IP, are lying about performance.
- svnt 2y agoThe question is more of will your customers agree to go along with this major architectural shift that sets you back on price-performance-power curves by at least five years and moves you out of the mainstream of board support packages, drivers, and everything else software-wise for phones. Also we should not pretend that ARM is just going to sit there waiting for RISC-V to catch up.
- tightbookkeeper 2y agoYes. This caveat is most clear. I am wondering about the question of performance raised in this thread,
- bhouston 2y ago> The question is more of will your customers agree to go along with this major architectural shift that sets you back on price-performance-power curves by at least five years and moves you out of the mainstream of board support packages, drivers, and everything else software-wise for phones. Embedded is moving to RISC-V where they have low performance needs. One example is the Espressif line of CPUs - which have shipped over 1B units. They have moved most of their offerings to RISC-V over the last few years and they are very well supported by dev tools: https://www.espressif.com/en/products/socs https://www.espressif.com/en/products/socs
- bluGill 2y agoWell you need several years to catch up - and those doing arm are not standing still. Same problem big software rewrites have, some are successful but it takes a large investment while everyone is still using the old stuff that is better for now.
- dagmx 2y agoMaking the chip isn’t an issue for them. It’s the software compatibility post facto.
- hajile 2y agoWe're not quite there yet. A bunch of mission critical stuff like SIMD were only added in the last 2-3 years. As it takes 4-5 years to design/ship high-performance chips, we still have a ways to go. Ventana Veyron looks interesting. Tenstorrent's upcoming 8-wide design should perform well. Qualcomm pitched making a bunch of changes to RISC-V that would move it closer to ARM64 and make porting easier, so I think it's an understatement to say that they are considering the idea. If ISA doesn't matter, why pay tons of money for the ISA?
- bhouston 2y agoIt is much more than just SIMD. I think RISC-V chips in the wild do not do things like pipelining, out-of-order, register renaming, multiple int/float/logic units, speculation, branch predictors, smart caching. I think all existing RISC-V chips in the wild right now are just simplistic in-order processors.
- avvvv 2y agoCould patents be one of the reason why? Genuine question.
- shash 2y agoAlmost all in-order processors will do pipelining, so that's there. Many are even multi-issue. Andes has an out of order core [1] and so does SiFive (though I don't know of many actual chips using these. [1] https://www.andestech.com/en/2024/01/05/andes-announces-general-availability-of-the-new-risc-v-out-of-order-superscalar-multicore-processor-the-andescore-ax65/ https://www.andestech.com/en/2024/01/05/andes-announces-gene... [2] https://www.sifive.com/cores/performance-p650-670 https://www.sifive.com/cores/performance-p650-670
- hajile 2y agoYou are wildly mistaken here. Back in 2016, BOOMv1 (Berkley Out-of-Order Machine) had pipelining, register renaming, 3-wide dispatch, branch predictor, caches, etc. A quick google seems to indicate that it was started in 2011 and had taped out 11 times by 2016 (with actual production apparently being done on IBM 45nm). They are on BOOMv3 now.
- qiqitori 2y agoThere is a chip out there that contains both an ARM and a RISC-V core, the RP2350. It's reasonable to assume that the ARM part and RISC-V part are manufactured in the same process. There are some benchmarks pitting the two against each other on e.g. this page: https://forums.raspberrypi.com/viewtopic.php?t=375268 https://forums.raspberrypi.com/viewtopic.php?t=375268 For a generic logic workload like Fibo(24), the performance is essentially the same (quote from above page): Average Runtime = 0.020015 Pico 2 Average Runtime = 0.019015 Pico 2 RiscV Note that neither core on the RP2350 comes with advanced features like SIMD.
- 05 2y agoIt's a Cortex-M33, a 32bit microcontroller core with no virtual memory. Are we really comparing microcontrollers to modern aarch64 processors?
- delfinom 2y agoYes? Because nobody has released a RISC-V MPU comparable to what you perceive as "moden" arm64 MPUs. RISC-V is simply a ISA and not a core. The ISA affects some of the core architecture but the rest is also implementor specific. High-end cores will take time to reach market. Companies with big guns like Qualcomm can most likely pump out if they wanted to, and will most likely be doing so in the future since they are pumping over $1 billion into the effort.
- kimixa 2y agoHow you design a core is very different based on if you're targeting ultra-low-power tiny microcontroller designs vs high performance and high power laptop/desktop-tier designs. And it's not been proven that RISC-V is a good match for the second group (yet). Remember it's sometimes very non-obvious what quirks of an ISA might be difficult until you actually try to implement it - one of the reasons ARM had a pretty much "clean sheet" rewrite in ARMv8 is things like the condition codes turned out to be difficult to manage in wide superscalar designs with speculative execution - which is exactly the sort of thing required to meet the "laptop-tier" design performance requirements. It may be they've avoided all those pitfalls, but we don't really know until it's been done.
- IshKebab 2y agoYou're confusing the ISA with the chip. Current RISC-V chips are slower than high performance ARM ones, but that's because you don't start by designing high performance chips! You start with small embedded cores and work your way up. Exactly the same thing happened with ARM. It started in embedded, then phones, and finally laptops and servers. ARM was never slow, they just hadn't worked up to highly complex high performance designs yet.
- wmf 2y agoyou don't start by designing high performance chips! You start with small embedded cores and work your way up. I disagree. For example, the first PowerPC was pretty fast and went into flagship products immediately. Itanium also went directly for the high end market (it failed for unrelated reasons). RISC-V would be much better off if some beastly chips like Rivos were released early on.
- snvzz 2y agoThe high end requires specifications that were not available until RVA22 and Vector 1.0 were ratified. First chips implementing these are starting to show up as seen in e.g. MILK-V Jupiter, which is one of the newest development boards in the market. With the ISA developed in the open, the base specs microcontrollers can target would naturally tend to be be ratified first, and thus microcontrollers would show up first. RVA22+V were ratified November 2021. With the ISA developed inside working groups involving several parties, some slowness would be unavoidable, as they all need to agree on how to move forward. Thus the years of gap until RVA22+V from the time the privileged and unprivileged specs were ratified (2019). RVA23 has just been ratified. This spec is on par with x86-64 and ARMv9, feature-wise. Yet hardware using it will of course in turn take years to appear as well.
- bhouston 2y agoIsn't the problem the lack of advanced features for executing the current ISA with speed? I thought RISC-V chips seen in the wild do not pipelining, out-of-order, register renaming, multiple int/float/logic units, speculation, branch predictors, multi-tier caching, etc. The lack of speed isn't really related to a few missing vector instructions.