14 ms·
How DRAM changed the world
- MichaelZuo 2y agoDennard scaling for SRAM has certainly halted, as demonstrated by TSMC’s 3nm process vs 5 nm. What’s the likely ETA for DRAM?
- wmf 2y agoNow? Prices have been flat for 15 years and DRAM has been stuck on 10 nm for a while.
- philipkglass 2y agoThat's overstating the flatness of prices. In 2009, the best price recorded here was 10 dollars per gigabyte: https://jcmit.net/memoryprice.htm https://jcmit.net/memoryprice.htm Recently DDR4 RAM is available at well under $2/GB, some closer to $1/GB.
- jychang 2y ago$1/GB? That's around the price SSDs took over from HDDs...
- ksec 2y agoNot soon as DRAM is mostly on older node. But overall cost reduction of DRAM is moving very very slowly.
- Salgat 2y ago5nm can hold roughly a gigabyte of SRAM on a cpu-sized die, that's around $130/GB I believe. At some point 5nm will be cheap enough that we can start considering replacing DRAM with SRAM directly on the chip (aka L4 cache). I wonder how big of a latency and bandwidth bonus that'd be. You could even go for a larger node size without losing much capacity for half the price.
- bgnn 2y ago5nm will never be that cheap. The performance benefit would be easily 2x or more though.
- Salgat 2y agoEven 15 years from now?
- crest 2y agoSRAM also requires more power than DRAM and the simple regular structure of SRAM arrays compared to (other) logic makes it possible to get good yield rates through redundancy and error correction codes so you could have giant monolithic dies, but information can't exceed the speed of light in a medium. There just isn't enough time for the signals to propagate to get the latency you expect of a L3 cache out of gigabytes (in relative terms) far away big dies containing gigabytes of SRAM. Also moving that the data would to perform computations without caching would be terrible wasteful given how much energy is needed just to move the data. Instead you would probably end up with something closer to the computing memory concept to map computation to ALUs close to the data with an at least two tier network (on-die, inter-die) to support reductions.
- Salgat 2y agoOh yeah this would definitely be something like L4 cache rather than L3 like AMD's X3D cpus. The expectation is as an alternative to DRAM (or as a supplement), kind of like what Xeon Phi did.
- deleted 2y ago[deleted]
- hajile 2y agoYears ago. DRAM uses a capacitor. Those capacitors essentially hit a hard limit at around 400MHz for our traditional materials a very long time ago. This means that if you need to sequentially read random locations from RAM, you can't do it faster than 400MHz. Our only answer here is better AI prefetchers and less-random memory patterns in our software (the penalty for not prefetching is so great that theoretically less efficient algorithms can suddenly become more efficient if they are simply more predictable). As to capacitor sizes, we've been at the volume limit for quite a while. When the capacitor is discharged, we must amplify the charge. That gets harder as the charge gets weaker and there's a fundamental limit to how small you can go. Right now, each capacitor has somewhere in the range of a mere 40,000 electrons holding the charge. Going lower dramatically increases the complexity of trying to tell the signal from the noise and dealing with ever-increasing quantum effects. Getting more capacitors closer means a smaller diameter, but keeping the same volume means making the cylinder longer. You quickly reach a point where even dramatic increases in height (something very complicated to do in silicon) give only minuscule decreases in diameter.
- aidenn0 2y agoIf that's the case, why haven't we switched to SRAM? Isn't it only about 4x the price at any given process node?
- RF_Savage 2y agoThat 4x the price does also explain why it has not happened.
- guerrilla 2y agoYeah but why don't we have like 500MB of SRAM per 8GB of RAM. Certain addresses could be faster, in the same way /dev/shm/ is faster.
- turtles3 2y agoThis is sort of the role that L3 cache plays already. Your proposal would be effectively an upgradable L4 cache. No idea if the economics on that are worth it vs bigger DRAM so you have less pressure on the nvme disk.
- cubefox 2y ago> Dennard scaling for SRAM has certainly halted, as demonstrated by TSMC’s 3nm process vs 5 nm. I don't think the latter (SRAM capacity remaining the same per area?) has anything to do with Dennard scaling.
- neom 2y agoI miss RAM. I feel like if you lived through that 90s RAM frenzy, you probably miss RAM too. It was crazy how quickly we move through SDRAM/DDR, prices dropped and you could make real increases in performance year over year for not much money. I'm sure some of it was the software being able to capture the hw improvements, but that certainly was my fav period in tech so far.
- IshKebab 2y agoNah the biggest jump in performance by far was SSDs. It was a huge step so software had no chance to "catch up" initially.
- szundi 2y agoIt's happening, Windows gets slower every year to adapt to SSDs.
- Gibbon1 2y agotinfoil hat on. I think Microsoft is making windows slow to prepare people for when they move everything on your computer to their cloud. tinfoil hat off.
- anticensor 2y agoThat's Wirth's law moved to a conspiracy theory level.
- deleted 2y ago[deleted]
- thr0w 2y agoGetting a new stick of RAM was so damn exciting in the 90s.
- myself248 2y agoAnd putting the old ones in a SIMM-stack to still use them on a new motherboard, because noone would be so crazy as to throw away good DRAM.
- metta2uall 2y ago"8K video recording" - does anyone really need this? Seems like for negligible gain in quality people are pushed to sacrifice their storage & battery, and so upgrade their hardware sooner...
- lightedman 2y agoI need more than 8K. I'm working at microscopic levels when I study minerals, I need as much resolution as I can possibly get, to the limit of optical diffraction.
- kstrauser 2y agoAre you actually recording movies of them though? Honest question. I hope I learn something about studying minerals!
- lightedman 2y agoYes. I do record videos for research purposes. Watching how a crystal reacts to various forms of radiation (primarily various bands of UV) gives me an idea of what impurities it might contain, or clues to composition from known emission spectra. That's recorded simultaneously through OBS with my voice doing a voiceover as I perform irradiation of the sample. Mineral goes into modified integrated sphere, sphere gets sealed, sample is illuminated, study begins.
- kstrauser 2y agoHuh! That sounds fascinating. I'd love to see something like that.
- lightedman 2y agoSome times I do live broadcasts for a group of hobbyists and degree-holding geologists. the bandwidth to do compressed 16K already exists for me, just not the tooling at the moment. Trying to show something that is literally one pixel at 400x magnification at 1080p is no fun. Even a few more pixels helps.
- seunosewa 2y agoThe article doesn't properly explain how DRAM is different from SRAM. DRAM has to constantly refresh itself in order not to 'forget' its contents.
- deleted 2y ago[deleted]
- praptak 2y agoYes, it totally misses the crucial and non obvious trade off which unlocked the benefits. The rest of the system has to take care of periodically rewriting every memory cell so that the charge doesn't dissipate. In fact it took a bit of time for the CPUs or memory controllers to do it automatically, i.e. without the programmer having to explicitly code the refresh.
- kstrauser 2y agoWhy would we use DRAM, then? It seems better not to have to refresh it all the time. (I think I more or less know, but I’d rather talk about it than look it up this morning.)
- deleted 2y ago[deleted]
- myself248 2y agoBecause SRAM is essentially a flipflop gate. It takes at least four transistors to store a single bit in SRAM, some designs use six. And current must continuously flow to keep the transistors in their state, so it's rather power hungry. One bit of DRAM is just one transistor and one capacitor. Massive density improvements; all the complexity is in the row/column circuitry at the edges of the array. And it only burns power during accesses or refreshes. If you don't need to refresh very often, you can get the power very low. If the array isn't being accessed, the refresh time can be double-digit milliseconds, perhaps triple-digit. Which of course leads to problems like rowhammer, where rows affected by adjacent accesses don't get additional refreshes like they should (because this has a performance cost -- any cycle spent refreshing is a cycle not spent accessing), and you end up with the RAM reading out different bits than were put in. Which is the most fundamental defect conceivable for a storage device, but the industry is too addicted to performance to tap the brakes and address correctness. Every DDR3/DDR4 chip ever manufactured is defective by design.
- WarOnPrivacy 2y agoupdated June 2024 Update: Today, marking the 56th anniversary...1966 Please forgive my pedantry but 58th. It was a busy year.
- asdefghyk 2y agoI have a recollection of a design where microprocessor reads were used to refresh DRAM contents. Late 1970s. I thought it was in a early 6800 Motorola book. Can find it now, or no mention of the technique, now. Would slow down program operation for sure. Maybe my recollection is wrong, not sure.