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Hazard3: 3-stage RV32IMACZb* processor with debug
- johndoe0815 2y agoThis is the RISC-V core used in the RP2350, the new Raspberry Pico 2 SoC.
- cpldcpu 2y agoIt's also an interesting juxtaposition, because it directly allows to benchmark the architectures in the same system environment. In the RP2350 it is possible to either use the RISC-V cores, the CM33 cores or even use one of each.
- IshKebab 2y agoI dunno if it will be that interesting due to area differences. Maybe if Raspberry publish the area stats too?
- cpldcpu 2y agoThey mentioned somewhere that they could not designate the actual area increase since it is part of the synthesized digital area. The area increase to include the RISC-V cores was negligible, apparently.
- doctorpangloss 2y agoIs a RISC-V core just the serial numbers filed off an ARM core?
- throwaway48476 2y agoThe core design isn't tightly coupled to the front-end ISA. AMD zen was going fo be offered in both x86 and ARM but the ARM front-end was canceled.
- Zeetah 2y agoI wonder if without the RISC-V cores the design was pad limited i.e. it had due area that wasn't used. So, they put in the RISC-V cores for no die cost. There will be some cost to test the RISC-V cores.
- phire 2y agoBut such benchmarks don't tell you anything at all about general ARM vs RISC-V performance. Those benchmarks would only tell you about those exact two cores, Cortex-M33 vs Hazard3. There are many other ARM and RISC-V implementations that are better and worse, depending on what customers need.
- jsheard 2y agoFun fact: to save space in the RP2350s ROM it contains a minimal ARM emulator for RISC-V, so that it can (mostly) use the same boot code for both architectures. https://github.com/raspberrypi/pico-bootrom-rp2350?tab=readme-ov-file#bootrom-details https://github.com/raspberrypi/pico-bootrom-rp2350?tab=readm... https://github.com/raspberrypi/armulet https://github.com/raspberrypi/armulet
- johndoe0815 2y agoAh, I read the rumor that there was an ARM emulator but didn't think it was open sourced. Thanks, that'll be a great example for my students...
- klelatti 2y agoJust to clarify > so ARM code is emulated (varmulet) on RISC-V As I initially read this the other way around.
- mrlonglong 2y agoNo support for floating point. It would have been nice to have that.
- cloudy_craggs 2y agoAny ideas about why the cores have been included? The best I can come up with is de-risking shipping RISC-V by doing a trial run. What are the rational use-cases for these cores, do they use less power?
- InvaderFizz 2y agoI would guess it is to: 1. Build out a RISC-V ecosystem for almost zero cost. The value-add is quite large for a segment of potential buyers as they get the same excellent ecosystem, but can target RISC-V as the uArch. 2. De-risk dealing with ARM in the future as their moves in licensing changes foretell a bleak future for licensees 3. Eventually a bargaining chip with ARM on licensing. "Give us favorable terms, or we drop ARM from this design"
- irdc 2y ago3b. Eventually, should ARM increase their prices, be able to produce a chip that only has the RISC-V cores but is otherwise 100% compatible with the RP2350. And thereby giving their clients the option of porting their software to RISC-V and shipping a single firmware image that runs on both older devices with the (now expensive) RP2350 and new devices with the (still cheap) RISC-V-only chip.
- jsheard 2y agoThe RP2350 already has an OTP bit which permanently disables the ARM cores when set, so they wouldn't even have to sacrifice their economies of scale in order to make that play. A RISC-V-only variant could be exactly the same hardware, just with the OTP pre-set at the factory.
- irdc 2y agoExactly. And should RISC-V turn out to have been a hype (which I don’t think, but I do recognise that convincing the various MBA types that think they make the world go ‘round is not a given) they can do the opposite. Which is nice for a chip they plan to make up to the 2040’s.
- Rochus 2y agoAmazing that it's apparently implemented in plain Verilog, not SystemVerilog; or did I miss something? Would be interesting to hear from the author what the motivation was for this choice.
- gchadwick 2y agoAt a guess it's because the author has been using Yosys for some formal verification work and maybe for doing some synthesis trials and it doesn't support system verilog natively. Though things are improving there: https://github.com/chipsalliance/synlig https://github.com/chipsalliance/synlig
- gchadwick 2y agoWould be interesting to know what verification they've done on this core. Given it's included as a bonus feature presumably they haven't done full DV on it. The repository has a testbench for running binaries, which includes the RISC-V compliance suite plus some usage of RISCV formal https://github.com/YosysHQ/riscv-formal https://github.com/YosysHQ/riscv-formal which is intriguing. Though nothing obvious of the level you'd need to close production level verification on a design.
- captn3m0 2y agoWould be an interesting experiment to run hazard3 against RISVuzz, that found the ghostwrite bug.
- alex7o 2y agoCan't wait to see how somebody hacks it to run code on all four cores at the same time. If this is technically/physically possible.
- p_l 2y agoIt's not - even assuming the cores don't share actual silicon, it's been mentioned that there aren't enough ports on the bus fabric to run 4 CPUs - each RISC-V + ARM pair shares common AHB port.