12 ms·
Optical PCIe 7.0 connection hits 128 GT/s
- taneq 2y agoGT/s = gigatranfers per second.
- 8n4vidtmkvmk 2y agoWhat's a transfer? That like a packet or a single bit?
- Arnavion 2y agoOne bit, but it's a bit of the underlying signal layer which has a 1-2% redundancy over the actual data. PCIe 2.0 and earlier encode 8b data in 10b signal. 3.0 to 5.0 encode 128b data in 130b signal. 6.0 and 7.0 do a more complicated thing: https://pcisig.com/blog/pcie%C2%AE-60-specification-webinar-qa-deeper-dive-flit-mode-pam4-and-forward-error-correction-fec https://pcisig.com/blog/pcie%C2%AE-60-specification-webinar-... Also the speed is per lane, eg an x8 slot / port / device is called that because it has 8 lanes, which all transfer in parallel.
- yjftsjthsd-h 2y agoEdit: Nope, I misread. As reply notes, 16GB/s/lane. So... That's about 16 terabytes per second per lane. AKA more bandwidth than I can imagine any use for, though I'm sure we will find ways to take advantage... (Seriously, that's enough to move 16 largish laptop drives every second, on a single lane.)
- Arnavion 2y ago>So... That's about 16 terabytes per second per lane. If you assume 1T/s = 1b/s, 128GT/s is 128Gb/s = 16GB/s, not 16TB/s
- yjftsjthsd-h 2y agoOops, yep, I misread that. Thanks for the correction
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- hughesjj 2y agoAssuming it was 16tb/s.... Imagine a JIT data lake loading stuff into main memory like brrr... Actually at that point, a pcie7 nvme would be faster than ddr6 https://www.pcworld.com/article/2237799/ddr6-ram-what-you-should-already-know-about-the-upcoming-ram-standard.html https://www.pcworld.com/article/2237799/ddr6-ram-what-you-sh... That said, per-pin, 16GB/s seems to be the same ballpark as contemporary (to pcie7) main or graphics memory..... Like, actually more if I'm reading this right? https://www.anandtech.com/show/21287/jedec-publishes-gddr7-specifications-pam3-ecc-higher-density https://www.anandtech.com/show/21287/jedec-publishes-gddr7-s...
- Dylan16807 2y ago> it's a bit of the underlying signal layer which has a 1-2% redundancy over the actual data. PCIe 2.0 and earlier encode 8b data in 10b signal. 3.0 to 5.0 encode 128b data in 130b signal. 6.0 and 7.0 do a more complicated thing Though the exact details of the overhead don't matter very much. They add 6% extra bits, good enough. The part I want to call out as complicated/confusing is that a PCIe 7.0 lane puts out a voltage 64 billion times per second, but because each voltage is based on two bits that counts as 128 billion "transfers".
- loeg 2y agoYeah, the overhead isn't a big deal now that the overhead is single digit. Back when it was 20% in PCIe 2 it was a much bigger discrepancy.
- Dylan16807 2y agoBack then they were adding the overhead on top of the baseline speed, not subtracting it. With 1 and 2 you got the full 1/4 and 1/2 gbps of data per lane, but then 3 was only .985 instead of 1. So I'd argue that 6% for PCIe 6 and 7 is the most meaningful the overhead has ever been.
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- lloeki 2y agoSo, it's still bits all the way down? Whether we're talking about app, IP, or LL it's always bits/s, each level bringing a cost due to encapsulation. And then at PHY there's baud. Is non-ISO unit "T" / "transfer" a marketing term or really specialised jargon? "transfer" just doesn't click in my mind, at best "a transfer" (countable) is about moving a sizeable aggregate chunk that has some semantic meaning, not a single fundamental quantum of information. Unrelated: "gigatesla per second" is such a mind-boggling unit.
- orthoxerox 2y agoIt's really specialized jargon that underscores the fact that it's raw bandwidth, not usable bandwidth.
- Arnavion 2y agoAlso, another common usage of transfers/second is with RAM. DDR5 6000MHz RAM is actually 6000MT/s, and the clock actually runs at 3000Hz ("DDR" == "double data rate").
- jaydeegee 2y agoA transfer is 1 action to the size of the width of the channel.
- pkaye 2y agoThen you have to define what an action is.
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- pdimitar 2y ago[flagged]
- jakeinspace 2y agoWhat do you think people come to this site for?
- jauntywundrkind 2y agoMarvell was recentlty showing off a a PCIe 6.0 Alaska-P retimer that's good for pcb, copper cable, & optical interconnect. Doesn't include optical transceivers but does show the growing interest in optical PCIe. https://www.servethehome.com/marvell-extending-pcie-gen6-reach-from-3-5-inches-to-meters/ https://www.servethehome.com/marvell-extending-pcie-gen6-rea... Right now optical seems exotic & expensive but we seem near a severe tipping point. Copper keeps facing increasingly channeling signal integrity challenges, requiring expensive & energy consuming retimers. Meanwhile we think we can keep scaling optical down, integrating silicon photonics, getting increasingly lower pJ/b energy costs. Without the range & signal integrity issues. Not super duper deep but this 2 year old Cadence blog post goes into it, and it seems indeed to be where things are heading. https://community.cadence.com/cadence_blogs_8/b/breakfast-bytes/posts/photonics-keynote https://community.cadence.com/cadence_blogs_8/b/breakfast-by...
- yjftsjthsd-h 2y agoSo I guess what this makes me wonder is: Why are we using electrical signals to connect the data lanes between components and computers these days, rather than moving everything to optical for data movement (obviously power would stay electrical, but that's already on separate lines)? I assume there's an element of cost, and once the photons get where they're going they have to be turned back into electrical signals to actually be used until such time as we get around to getting pure light based computers working (someday but not yet...), but that must not overwhelm the advantages or we wouldn't be looking at this being developed.
- cma 2y agoSince thunderbolt is related to PCIe, there's this that goes into copper vs optical there: https://en.wikipedia.org/wiki/Thunderbolt_(interface)#Copper_vs._optical https://en.wikipedia.org/wiki/Thunderbolt_(interface)#Copper...
- watersb 2y agoIntel's product name foe Thunderbolt was initially was "Light Peak".
- throwaway48476 2y agoI believe it was originally supposed to be optical.
- asadhaider 2y agoSo we're moving towards crystals from Stargate? Neat
- AceJohnny2 2y ago> I assume there's an element of cost, and once the photons get where they're going they have to be turned back into electrical signals to actually be used until such time as we get around to getting pure light based computers working (someday but not yet...) You got it. We can't make optical transceivers as good as electrical ones. Not as small or power-efficient. They require significantly different fabrication processes, and we don't know how to fab them into the same chip as electrical ones. I mean: you can either have photonics, or performant digital (or analog) electronics. We've gotten really, really good at making small electronics, per the latest tech coming out of Intel & TSMC. We are... not that good at making photonics.
- mistyvales 2y agoHere I am still on PCI-E 3.0...
- Arnavion 2y agoMost hardware (NVMe drives, GPUs, etc) doesn't run at more than 4.0 speeds anyway. The primary advantage of 5.0 and higher is that it'll allow that hardware to use fewer CPU lanes, eg what requires 4.0 x4 could use 6.0 x1.
- accrual 2y agoIt kinda worked that way in the past too. IIRC, newer AGP graphics cards would be keyed for 4x or 8x slots but would barely use more bandwidth than the original 2x slots provided.
- lightedman 2y agoWe didn't really bottleneck AGP8X until nVidia dropped the 200 series GeForce GPU. Then PCI-E was pretty much a requirement.
- steelbrain 2y ago> eg what requires 4.0 x4 could use 6.0 x1 FWIW, this is only true for newer hardware. ie if you plugged in a pcie gen3x16 device into a pcie gen4x8 slot, although the bandwidth provided is in the same ballpark, the device will only run at pcie gen3x8. So we'll need until the devices upgrade themselves to gen4 in this scenario to make use of higher bandwidth.
- TZubiri 2y agoGigaTeras?
- SebJansen 2y agoGigaTransfers. 128 GT is 8192 Gbps
- lights0123 2y agoFor DDR RAM, which uses 64 parallel lines. PCI-E transmits one bit per transfer, which has its practical bandwidth reduced after error correction.
- banish-m4 2y agoDamn. Just put together 2 7900X3D + H13SAE-MF + RTX 4070 Ti SUPER + 100GbE-SR4 NICs with PCIe 5.0 and ATX 3.0. Mostly for bare-metal NIC load testing. Already obsolete. In other news, I'm getting a Xeon with 4 whole GiB of DDR2 ECC RAM shipped from China that has 3 ISA slots. ;D
- vardump 2y agoWhat kind of 100GbE throughput you’re getting?
- banish-m4 2y agoThe invisible kind because not all the parts have arrived because WiredZone and Next International are terrible Supermicro VARs to be avoided.
- automatic6131 2y ago>7900X3D What purpose could this possibly serve? Enjoying worse performance than a 7900X?
- banish-m4 2y agoWhat's your problem, bucko? 2x the L3 and a lower price tag.
- automatic6131 2y agoBut that L3 is only on 6 of the cores, the other 6 don't have it. The non-3d cores can clock like 10% higher or more.
- justsomehnguy 2y ago> In other news, I'm getting a Xeon with 4 whole GiB of DDR2 ECC RAM shipped from China that has 3 ISA slots. ;D There is no DMA there, so your Sound Blaster wouldn't work [from the box].
- Taniwha 2y agoIt's worth being clear about what Cadence are announcing here (Cadence sells VLSI tooling and libraries) - they have 2 things: - cells for a chip to send/receive at 128Gb/s - this solution requires 8 of them running in parallel (like 8 PCIe lanes) - a module that takes 8 lanes in/out and drives/receives a single fiber
- Copenjin 2y agoCan't they use proper units? I refuse to even read this.
- adastra22 2y agoThese are the standard and correct units.
- Copenjin 2y agoNo, GT/s is not, regardless of the downvotes, please point me to the standard that defines them if I'm wrong. Let's keep using the boring GB/s since we are still talking about data.
- adastra22 2y agoThe PCIe standard uses GT/s: https://pcisig.com/specifications/pcie-70-specification-version-03-now-available-members https://pcisig.com/specifications/pcie-70-specification-vers... This is not the same as Gb/s. There's a few percentage points difference due to error correction.
- Copenjin 2y agoThanks.
- mrweasel 2y agoAn once that becomes generally available operating systems will eat the bandwidth in an instance and any speed-up to be gained on a desktop will be completely negated. It seems like we're stuck at a pre-set level of latency, which is just within what people tolerate. I was watching a video of someone running Windows 3.11 and notice that the windows closes instantly, which on Windows 10 and 11 I've never seen there NOT be a small delay between the user clicking close and the window disappearing.
- vladvasiliu 2y ago> which on Windows 10 and 11 I've never seen there NOT be a small delay between the user clicking close and the window disappearing. Isn't that delay related to the default animations? On my particular machine with animations disabled, if I click the minimize button, the window disappears instantly. This is your standard win11 on a shitty enterprise laptop running some kind of 11th gen i7u with the integrated graphics and a 4k external display. Maximization is sometimes janky, but I guess it's because the window needs to redraw its contents at the new size.
- PlutoIsAPlanet 2y agoModern operating systems render to buffers on the GPU and then composite them, which I would guess adds some latency (although likely unnoticeable).
- LoganDark 2y agoIt's not unnoticeable. Ever notice how on Windows, when you start to drag a window, your cursor disappears for a frame? That's Windows replacing your cursor with a software-rendered one so it doesn't appear ahead of the window. But drag anything else (i.e. browser tabs, text highlighting) and you'll quickly notice it lagging behind the cursor. Why? Because the cursor is a hardware overlay that can be moved before the composition is actually complete. The composition lags one frame behind. In other words, the price of the compositor is lagging one frame behind. That may not sound like much, but it is, especially when most displays are only 60 FPS. Of course, it's only one of the contributing factors to the total latency of things like keystrokes: https://danluu.com/input-lag/ https://danluu.com/input-lag/
- gtirloni 2y agoHow much of this article is written by the author instead of Cadence itself? The use of certain adjectives to describe how excellent some numbers are seems weird coming from a generic news editor. I don't know if I can trust this is as groundbreaking as it sounds.
- kees99 2y agoAlso, very sparse on technical details. Even basics are missing, like - what's optical signal like? CWDM? multiple polarizations? QAM? How many fibers? I mean - one can build a 16-fiber, CWDM16 monstrosity that would transport an 8x 128GT/s PCIe using mere 8 Gbit/s per channel - all of which is technology that was "groundbreaking" circa 2005.
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