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Intel Unveils Lunar Lake Architecture
- DeathArrow 2y ago>Intel Core product, the Lunar Lake SoC platform also includes up to 32 GB of LPDDR5X memory on the chip package itself What if you need 64 GB of RAM?
- kalleboo 2y agoThen you don't buy a "Low Power Mobile SoC" but a more powerful chipset
- ac29 2y agoBuy something else? Meteor Lake supports up to 96GB, and I assume AMD has something that supports 64GB+ as well. Lunar Lake is specifically targeted towards power efficient laptops, there are no desktop chips, or desktop-class mobile chips. Its being positioned for Macbook Air competitors, a device which maxes out at 24GB RAM.
- KingOfCoders 2y agoIt will end like Apple, an M3 Pro has up to 36gb of memory and an M3 Max from 48gb of memory. You get getter performance/watt but you can't upgrade. It depends on what you want.
- hulitu 2y ago> What if you need 64 GB of RAM? You're out of luck.
- diavolodeejay 2y agoTIL that ram affects wifi performance by creating interferences
- bjoli 2y agoIf you have external antennas you can (or at least could) actually try this. Having the RAM just behind the antennas (by holding them in an open case) with a clear line of sight to the router produced significantly worse results than moving the antenna 30cm in either direction. I can't remember which WiFi generation I was testing this with but I remember seeing something like a 40% reduction, worst case.
- mschuster91 2y agoAnything RF is deep wizarding lore, a world filled with wonders unexplainable to laypeople. The effect is well known, and the reason why if you open up your average phone, there will always be a ton of shielding around components. All the high speed buses can and do create lots of side emissions... so in order to allow a phone to function with its extremely tiny bunch of antennae in direct proximity to the chips, all components get shielded from each other. In desktops and even most laptops however, the high-speed (and thus high-frequency) chips and their clock traces are very far away from the wifi/bt antennae, so for a long time manufacturers could get away with not shielding anything, just taking care about ground planes, trace length and impedance matching and spacing. Nowadays, with buses getting ever faster and faster (to the point where analog design criteria take over priority), I think we'll start seeing shielding rather sooner than later, and we're already seeing CAMM modules getting implemented in devices for the same purpose. Side note: that's also why you're not supposed to operate a computer's parts without a case at all or with a partially open cases. The case itself acts like a faraday cage.
- nubinetwork 2y ago4P4E and no HT? Hard pass.
- hedgehog 2y agoWhat workloads benefit enough from HT to justify it in a laptop?
- adgjlsfhk1 2y agoMost things (other than highly optimized HPC) benefits a ton from hyper threading. Code that's unoptimized (e.g. everything web/interpreted languages like python/JS) spends all its time chasing pointers which means that your cores are doing a whole lot of nothing. Hyperthreading means that you can run twice as many applications per core which means that while one thread is waiting for data from RAM, the other thread can utilize the execution units. This also helps power consumption since if you can consolidate all the tasks onto fewer cores, you can put the other cores to sleep and save power.
- dumbo-octopus 2y agoThis isn’t really true. In JS, the JIT can optimize many routines to be much more CPU bound than “just pointer chasing” would have you believe. And of course in Python the bulk of your time should be spent in native code. Whether it actually is is a different question.
- gpderetta 2y agoIf a load is intrinsically pointer chasing (as it is the case for a lot of non-compute software), there isn't much an optimizer can do. That's true even for native code.
- dumbo-octopus 2y agoThat may be the case, what I’m contesting is this distinction made between JS/Python and other languages.
- mahkeiro 2y agoIntel fully using TSMC for this generation is quite something!
- automatic6131 2y agoThey're making the interconnect themselves. But that very much sounds like I'm coping on their behalf. TSMC for all the logic and IO though.
- baq 2y agoThe consumer needs Intel to get back to somewhere within reach of competitive semi manufacturing. Fingers crossed though the past decade doesn't inspire hope...
- DebtDeflation 2y agoIntel never recovered from the 10nm debacle of 2015-2020.
- wmf 2y agoIntel 3 is supposed to be shipping as of today.
- JeremyNT 2y agoWhat a disaster! I hope this is the bottom, and that there's enough expertise left at Intel to save the company (and I guess enough political will in Washington to subsidize it). The world deserves competition in this space.
- mlboss 2y ago> the Lunar Lake SoC platform also includes up to 32 GB of LPDDR5X memory on the chip package itself Is this similar to Macbook M series chip with shared memory ? Will this allow intel chips to run local llms efficiently ?
- dagmx 2y agoIn theory, that’s how Intel already is but the memory accessible to the GPU is capped at conservative values . The other issue is that traditionally the integrated GPU has been quite anaemic.
- DeepYogurt 2y ago> Will this allow intel chips to run local llms efficiently ? 32GB might not be enough for everything
- Dylan16807 2y agoMicrosoft's local copilot requirements are 16GB of memory so it's plenty for that.
- deleted 2y ago[deleted]
- AnthonyMouse 2y ago> the Lunar Lake SoC platform also includes up to 32 GB of LPDDR5X memory on the chip package itself. This is arranged as a pair of 64-bit memory chips, offering a total 128-bit memory interface. As with other vendors using on-package memory, this change means that users can't just upgrade DRAM at-will, and the memory configurations for Lunar Lake will ultimately be determined by what SKUs Intel opts to ship. In other words, even though it's on-package, the width of the memory interface is the same as previous generations. They also exclude upgradability unnecessarily, because even with on-package memory you can still support adding memory through slots. For example, the Xeons with on-package HBM allow this. This decision by Intel seems specifically designed to screw the customer by forcing them to buy a new CPU (or computer) in order to upgrade the memory, without even providing the countervailing benefit that Apple gets from doing it that way. (Note that Apple too unnecessarily prevents adding memory at the traditional level of performance. Cache hierarchies are a thing, if you're not trying to screw the customer.)
- simple_quest_9 2y agoI'm trying to learn about ISAs. And, after taking a class and watching a whole bunch of RISC vs CISC videos, I still don't know 'why' Apple Silicon is faster at a lower power consumption than Intel's chips. Can someone tell me?
- lights0123 2y agoA big factor is that Apple buys out all of TSMC's capacity for new process nodes, so they get the smallest transistors that run at lower power and higher speeds.
- dagmx 2y agoPeople say this, but it’s a trite trivialization of the architectural choices made beyond just the ISA. When AMD/intel have moved to the same or comparable nodes, they’re not catching up for perf/watt. Lunar Lake will be on the same N3E as M4, so we’ll have to see how it compares.
- AnthonyMouse 2y ago> When AMD/intel have moved to the same or comparable nodes, they’re not catching up for perf/watt. They are though? If you compare the Apple and AMD processors that are both on e.g. TSMC 5nm, the AMD ones have if anything better performance per watt. Compare the 7945HX3D to any Apple CPU on the same 5nm process with a similar TDP and the 7945HX3D will generally have similar if not better performance. But people keep doing comparisons right after Apple is the first to release a CPU on a new TSMC process, and naturally if you don't compare like with like, the newer process is more efficient. Another reason people keep getting confused is that AMD isn't afraid to go back and release updated models of older cores on their original process nodes. So for example the 7730U is from 2023, it's just a year old, but it's Zen 3 on the 7nm process they've been using since 2019. Meanwhile the "real" 2023 release was Zen 4 on 4nm (e.g. 7840U), but don't pick the wrong one to do your comparison.
- KingOfCoders 2y ago
- tedunangst 2y ago> Another striking advance is the migration in the P-core database from a 'sea of fubs' to a 'sea of cells'. This process of updating the organization of the P-cores substructure moves from tiny, latch-dominated partitions to more extensive and ever larger flop-dominated partitions that are very agnostic as things go. I like to pretend I know a thing about CPU design, but I have to admit, I have no idea what's going on here.
- p1esk 2y agoFUB: Functional Unit Block. It seems that they are moving from higher level (larger) building blocks to lower level (smaller) building blocks to increase efficiency.
- TeMPOraL 2y agoThe second part of the quote says they're moving from "tiny" to "more extensive" partitions though; it feels confusingly contradictory.
- sameerds 2y agoI read it as "fubs were small partitions, but now with the latch boundaries dissolved between fubs, the partitions are bigger (containing flops from many fubs)".
- fanf2 2y agoMy flop partition is very agnostic about understanding that sentence, as things go.
- santiagobasulto 2y agoChip design is SUCH an advanced topic. It's potentially one of the most advanced human disciplines at the moment. I have a friend[0] that is doing his Electronics Engineering masters in Germany (very prestigious engineering university) and they're studying a freaking Pentium 4. Even for them the cutting edge chip design is black magic. [0] Ultimate frisbee teammate.
- shrubble 2y agoMy thinking is that we may be seeing MSFT working to commoditize CPUs and in the process end up strengthening their position while weakening ARM, AMD, and Intel's positions. In the past MSFT was always wedded to x86 but now with other ISAs coming, that presumably Windows 11 can be ported to...
- jayb_oz 2y ago> In the past MSFT was always wedded to x86 ?? WindowsNT shipped on x86, Alpha, and MIPS. Then got ported to X64, PowerPC and Itanium. For the NT line, historically Microsoft was very supportive of other ISAs. The market wasn't. (I worked on applications supporting a number of those. x86/x64 won the price/performance war).
- shrubble 2y agoNo one bought it on those alternative ISAs, however. The Alphas and MIPS vendors had a port but what percentage of those systems ended up running a Unix? This time it is different since DOS and 16bit Windows is out of the picture. This time you have multiple vendors/OEMs actually shipping e.g. Snapdragon-based Windows systems. Lenovo might make money selling such laptops, but over time MSFT will be the largest beneficiary of the "CPU wars".
- The_Colonel 2y agoThere was already Windows on ARM in not so distant past, but it failed. I'm not convinced this time it will be different.
- Marsymars 2y agoThere was Windows RT, which failed, but the current Windows on ARM platform has been a thing since 2017. The first few Win10 on ARM devices aren't upgradeable to Windows 11, but anything since the Snapdragon 850 in 2018 is fully supported by Windows 11: https://learn.microsoft.com/en-us/windows-hardware/design/minimum/supported/windows-11-supported-qualcomm-processors https://learn.microsoft.com/en-us/windows-hardware/design/mi... I guess it could still fail, but to me it seems a bit weird to be predicting the failure of a 7 year-old platform just when it's starting to see a real uptick in momentum.
- SunlitCat 2y agoAlthough memory bandwidth is still a limiting factor, I still hope those improvements at the integrated gpu ship over to their desktop counterpart. AMD seems to get at it already. (Yes Yes, I know I know. But I am still dreaming to fit a system capable to play at least a few games into a mini itx case without needing to add a dgpu. One can dream, eh? :)
- kohlerm 2y agoWhat is the memory bandwidth? I could not find any numbers ..
- SunlitCat 2y agoSorry, I worded my comment not correctly! I meant in general like in for gaming uses, integrated gpus are limited by the memory bandwidth of the DDR memory bus compared to the high bandwidth memory on dgpus.
- eigenspace 2y agoIt’s sounding like AMDs high-end mobile processors will probably do what you want mid-to-late next year. Look up “Strix Halo” (not Strix Point, that’s this year). They’re reportedly going for a 256 bit memory interface, and a way bigger GPU than what’s normal for integrated graphics.
- SunlitCat 2y agoThat's something I am really looking forward to. I mean, AMD (together with Intel!) was already there, with their KabyLake-G lineup. Intel processor and AMD Vega (although it was Polaris Arch, I think) Graphics together along with 4 GB of HBM 2 graphics memory. Or all those custom APUs, AMD is doing since quite some time, like way back in 2018 for that Chinese computer / game console thingy (Subor Z+). Or for the new wave of handheld game consoles. And last but not least for the Playstation / XBox. That packaged onto a Mini-ITX mainboard along with 32 or 64 GB of RAM would be quite nice.
- acje 2y agoI look forward to the decline in interest in generative ML. There is a screaming need for secure online services to enable democracies to face off the threat from authoritarian regimes. To do this we need hardware that enables actors as in actor model with truly private state, not sandboxed where there is an external entity that can observe its state. Today pretty much all designs has a perverse von Neumann architecture where state is shared across different compute devices like network controllers and management engines. And the software stack is more of the same sandboxing. Apple includes a Secure Enclave on its SoC where you may only communicate with it by sending messages like a proper actor, but why aren’t servers made entirely of secure enclaves? If the memory of each enclave was private by design in hardware it shouldn’t be necessary to encrypt it.
- TeMPOraL 2y agoHow would that empower democracies more than authoritative regimes? The technologies you mention are means of control, and are used as such. Secure computing doesn't help you when the regime owns the keys (or can coerce them out of the vendor). I may very much be wrong about it, but intuition and experience tells me that means of control usually empower authoritarian parties first and foremost, unless fully owned and operated by individuals - which, in computing, is very much counter the trend and the zeitgeist.
- acje 2y agoGood question and I don’t have a good answer. My intuition is that democracies are more dependent on transparency and that lower complexity and higher security would enable more distribution in control.
- TeMPOraL 2y agoI intuitively agree on transparency being important for democracies, but then I see "lower complexity" and "transparency" as both being opposed to "higher security". Taking for example the secure enclave you mention, its whole point is to bolster security through removing transparency via a complex hardware and software system.
- adrian_b 2y agoBased on the instruction set extensions supported, the design of Lunar Lake has been started later that the designs of Arrow Lake and Arrow Lake S. When first announced, Lunar Lake was supposed to be manufactured by an Intel CMOS process that will be available only in 2025 (18A). At some point, Intel has decided to retarget Lunar Lake for the TSMC "3 nm" process, and it appears that this decision has allowed them to be ready for product launch much earlier, so it might be launched before Arrow Lake and Arrow Lake S (the latter of these 2 is a desktop CPU that will also be made in the TSMC "3 nm" process, according to rumors). At Hot Chips 2024, Intel is scheduled to make a more detailed presentation of Lunar Lake.
- mmaniac 2y agoAlso, apparently low end (mobile?) Arrow Lake CPUs will use 20A while higher end will use 3nm. It's not looking good for Intel foundries.
- ac29 2y agoXeon 6E launched this week on the Intel 3 process. Benchmarks of production silicon look good for performance but especially good for performance per watt. Definitely competitive with AMD.
- nottorp 2y agoIntegrated ram, limited to 32 Gb. I wonder if they'll make 4 Gb SKUs to outdo Apple at their own game... Also, will the spying coprocessor, sorry, "AI" coprocessor, have a hardware off switch that will cut the power to that part of the CPU?
- Sakos 2y agoI'm so tired of soldered components. The performance and power benefits are simply not good enough to justify producing millions of landfill-destined devices and high costs for consumers.
- johnny22 2y agoI don't think soldered components would have been a big deal were the amounts enough. 32gb soldered on say 7 years ago would last you a long time. If they're gonna solder, they need to stop skimping.
- nottorp 2y agoOne other major problem with soldering is only the most common SKUs are in stock, at least if you're in a smaller market. I mean, I hope the US is different, not sure if that's true. If you want to future proof and max out the ram you have to wait. And if you need an emergency hardware replacement, you're screwed.
- fomine3 2y agoApple M3 supports up to 24GB of RAM so it's not so bad.
- nottorp 2y agoApple supports up to 96 or 128 gb in laptops though. Why do you compare just with the entry level SoC? That doesn’t make them any less assholes (cough ram pricing). I’m predicting that Intel will try to outcompete them at assholery though.
- ThePhysicist 2y agoAnyone got an estimate for when we might see new Thinkpads with these chips? End of this year? I'm not unhappy with my current gen 3 T14 but if I could have a device that's closer to my Macbook Pro M1 in performance and efficiency I'd be willing to upgrade, as I still like Linux much more than MacOS.
- MaKey 2y agoWhy Intel instead of AMD? Just curious.
- stqism 2y agoAttended both keynotes, but the data I’ve seen suggests Intels offerings are higher IPC + lower power VS the respective AMD AI CPUs.
- deaddodo 2y agoIntel themselves claim 45 TOPS (IPC isn't a thing in NPUs) coming from their NPU. AMD didn't reveal the chip total of the new Ryzen series, but their NPU gets 50 TOPS. The only reason Intel's numbers are so much higher ("120 TOPS!") is that Intel included their chip total (what the GP dies can achieve, but at far lower power efficiency) with the NPU numbers, AMD doesn't include this. Presumably their GP cores would be able to achieve similar numbers. Given that AMDs NPUs were already ~78% more power efficient than Intel's and both are claiming ~50% power efficiency increases, I'm not sure why there would be a big upset here. Not really defending AMD here, but they have been investing hard into NPUs for about four-five generations now, while Intel only really hopped on the bandwagon last generation. Unless you just believe Intel has the best engineers in the world, period; there's no reason to believe they would close the gap that quickly.
- aphexairlines 2y agoNot a Thinkpad and not Intel, but that already seems attainable with the asus G14 (AMD 8945HS + NVIDIA 4070) or the upcoming asus zenbook S16 (AMD HX 370).
- fariszr 2y agoA lot of the efficiency improvments depend on the new thread scheduler in Windows 11. I doubt these chips are going to be great or at least, as efficient in Linux as they are in Windows 11. AMD going for Zen5 and Zen5 is exactly to avoid this issue and the need for complex scheduling algorithms.
- eigenspace 2y agoI’m sure support for heterogeneous CPU scheduling will continue to improve on Linux too. Intel’s server chips have little cores too, and those servers are overwhelmingly running Linux, so they have a clear reason to continue to help support scheduling improvements in Linux as well.
- wmf 2y agoServers don't have heterogeneous cores.
- ac29 2y agoCompared to the previous generation, scheduling should be easier. Meteor Lake has P Cores with SMT, E Cores, and Low Power E Cores. Lunar Lake just has P Cores (no SMT) and E Cores.