8 ms·

The quote in there mentions “rate of iteration”, which given the noise Qualcomm were making makes me speculate Qualcomm are planning on forking RISCV to be more

The quote in there mentions “rate of iteration”, which given the noise Qualcomm were making makes me speculate Qualcomm are planning on forking RISCV to be more arm64ish and Google would not want to be maintaining both that and vanilla RISCV in this until the dust settles. It is something like that or they really are removing it.

snvzz 3y ago
It's the other way around. Support for Qualcomm's incompatible platform is being removed[0]. 0. https://news.ycombinator.com/item?id=40212173 https://news.ycombinator.com/item?id=40212173
themiddleupper 3y ago
I suspected it was not good news for RISC V when Qualcomm got involved. They are going to split the RISC V ecosystem.
- deleted 3y ago
  [deleted]
- Pet_Ant 3y ago
  > They are going to split the RISC V ecosystem. Part of the DNA of RISC-V is to provide a basis from which a million flowers can bloom. Instead of homebrewing, you can reuse RISC-V and make tweaks as you need... if you really do need a custom variant. Think of it as English, a common substratum from which there are lots of mostly interoperable dialects. This is what happened with Unix. Now if we want a mainstream consumer then we will need a dominant strain or two. The RISC-V foundation is doing that with the RVA23 profiles etc, but if there is a few major ones that should be navigable. Linux had support for PC-98[1] which was a Japanese alternate x86 platform. The changes I've seen proposed by Qualcomm don't seem drastically different [2], and could be incorporated in the same binaries with sniffing the supported features. The semantics are what are important, and it's not different there at all. Could be supported with trap and emulate [1] https://en.wikipedia.org/wiki/PC-98 https://en.wikipedia.org/wiki/PC-98 [2] https://lists.riscv.org/g/tech-profiles/attachment/332/0/code_size_extension_rvi_20231006.pdf https://lists.riscv.org/g/tech-profiles/attachment/332/0/cod...
  - Tuna-Fish 3y ago
    The code size reduction instructions are an extension that will go through and will eventually be supported by everyone, and is not the bone of contention here. They are designed to be "brown-field" instructions, that is, fit into the unimplemented holes in the current spec. The reason the spec is going to split is not them, but the fact that Qualcomm also wants to remove the C extension, and put something else in the encoding space it frees.
    - Pet_Ant 3y ago
      Hmm, that seems like a mistake because C allows for instruction compression with low cost to decode that is perfect for embedded use which is a big part of the RISC-V usage now. That said, if they implemented C, and then had their replacement toggleable with a CSR that would still be backwards (albeit not forwards) compatible so that'd only be an issue if Qualcomm RISC-V binaries become dominant, but I don't think binaries are gonna be that dominant outside of firmware going forward, and any that are will be from vendors that will multi-target.
      - phkahler 3y ago
        >> Hmm, that seems like a mistake because C allows for instruction compression with low cost to decode that is perfect for embedded use which is a big part of the RISC-V usage now. It may be low cost to decode a compressed instruction, but having them means regular 32-bit instructions can cross cache lines and page boundaries. My own thought is that there should be a "next" version or RISC-VI that is mostly assembler-level compatible but changes all the instruction encodings to be more sane. What that means exactly is still a bit fuzzy, but I am a fan of immediate data being stored after the opcode.
        __s 3y ago
        yes, was curious why compression format didn't require 1. non compressed instructions are always 4 byte aligned (pad a 2 byte NOP if necessary, or use uncompressed 4 byte instruction to fix sizing) 2. jump targets are always 4 byte aligned (which exists without C, but C relaxes) This avoids cache line issues & avoids jumps landing inside an instruction. Can consider each 2 compressed instructions as a single 4 byte instruction Bit redundant to encode C prefix twice, so there's room to make use of that (take up less encoding space at least by having prefix be 2x as long), but not important
- Tuna-Fish 3y ago
  The solution to this is not to split, but just follow Qualcomm. Their vision for the future of the ISA is simply much better than SiFive's. Right now, most devices on the market do not support the C extension, and any code that tries to be compatible does not use it. Qualcomm wants to remove it because it is actively harmful for fast implementations, and burns 75% of the entire encoding space, which is already extremely tight. SiFive really wants to keep it. The solution to fragmentation is to just disable the C extension everywhere, but SiFive doesn't want to hear that.
  - camel-cdr 3y ago
    > most devices on the market do not support the C extension Name one that doesn't, it's exactly the opposite (for 64-bit).
    - GeorgeTirebiter 3y ago
      Maybe you've found the solution: RV32 must have the C extension. RV64 and RV128 must NOT have the C extension. Problem solved?
      - camel-cdr 3y ago
        No I meant, that for 64-bit CPUs virtually every available one supports the C extension.
  - sitkack 3y ago
    > Right now, most devices on the market do not support the C extension This is not true and easily verifiable. The C extension is defacto required, the only cores that don't support it are special purpose soft cores. C extension in the smallest IP available core https://github.com/olofk/serv?tab=readme-ov-file https://github.com/olofk/serv?tab=readme-ov-file Supports M and C extensions https://github.com/YosysHQ/picorv32 https://github.com/YosysHQ/picorv32 Another sized optimized core with C extension support https://github.com/lowrisc/ibex https://github.com/lowrisc/ibex C extension in the 10 cent microcontroller https://www.wch-ic.com/products/CH32V003.html https://www.wch-ic.com/products/CH32V003.html This one should get your goat, it implements as much as it can using only compressed instructions https://github.com/gsmecher/minimax https://github.com/gsmecher/minimax
Dylan16807 3y ago
> to be more arm64ish I have a hard time picturing what this means. There's so much flexibility in implementing a core; what would they want to change in the ISA to make them like it better in a non-negligible way?
- fidotron 3y ago
  Prior discussion includes https://news.ycombinator.com/item?id=37996820 https://news.ycombinator.com/item?id=37996820
- Tuna-Fish 3y ago
  Mainly, richer addressing modes. SiFive designed RISC-V to have braindead-level simple addressing modes, with the idea that you use 2-4 normal alu ops to do addressing instead of a single op with a more complicated addressing mode. Then, to reduce the horrible impact this has on code size, they introduced the C extension that burns 75% of the encoding space of 32-bit instructions on 16-bit instructions, but this is still only a bandaid and a much weaker solution than having better addressing modes in the first place.
  - camel-cdr 3y ago
    It's not as black and white as you portray it. Both sides of the argument agree that high-performance implementations are doable and not hindered much buy both, you can watch the debate in the profiles SIG zoom meetings. I think the real dispute was how the opcode space and code density will evolve when more and more extension will need to be added. Will more 32 opcode space and aligned 64 bit instructions but no 16 and no 48 bit instructions in the longterm be a better choice than fewer 32 bit instructions, but 16/48/64 bit instructions? Qualcomm is also currently involved in the Combined Instructions SIG, and proposed a few instructions in that vain: https://docs.google.com/spreadsheets/d/1dQYU7QQ-SnIoXp9vVvVjS6Jz9vGWhwmsdbEOF3JBwUg/edit#gid=0 https://docs.google.com/spreadsheets/d/1dQYU7QQ-SnIoXp9vVvVj.... Notice that these are currently very mild combined instructions, like BEQI, or CLO, which are unlikely to be cracked into uops compared to more complex addressing modes (e.g. apple silicon needs to crack pre/post increment load/stores). BTW, this article is actually about removing Qualcomm specific stuff from android, see: https://lists.riscv.org/g/sig-android/topic/105816077#msg389 https://lists.riscv.org/g/sig-android/topic/105816077#msg389

snvzz 3y ago

It's the other way around. Support for Qualcomm's incompatible platform is being removed[0]. 0. https://news.ycombinator.com/item?id=40212173 https://news.ycombinator.com/item?id=40212173

themiddleupper 3y ago

I suspected it was not good news for RISC V when Qualcomm got involved. They are going to split the RISC V ecosystem.

deleted 3y ago
[deleted]
Pet_Ant 3y ago
> They are going to split the RISC V ecosystem. Part of the DNA of RISC-V is to provide a basis from which a million flowers can bloom. Instead of homebrewing, you can reuse RISC-V and make tweaks as you need... if you really do need a custom variant. Think of it as English, a common substratum from which there are lots of mostly interoperable dialects. This is what happened with Unix. Now if we want a mainstream consumer then we will need a dominant strain or two. The RISC-V foundation is doing that with the RVA23 profiles etc, but if there is a few major ones that should be navigable. Linux had support for PC-98[1] which was a Japanese alternate x86 platform. The changes I've seen proposed by Qualcomm don't seem drastically different [2], and could be incorporated in the same binaries with sniffing the supported features. The semantics are what are important, and it's not different there at all. Could be supported with trap and emulate [1] https://en.wikipedia.org/wiki/PC-98 https://en.wikipedia.org/wiki/PC-98 [2] https://lists.riscv.org/g/tech-profiles/attachment/332/0/code_size_extension_rvi_20231006.pdf https://lists.riscv.org/g/tech-profiles/attachment/332/0/cod...
- Tuna-Fish 3y ago
  The code size reduction instructions are an extension that will go through and will eventually be supported by everyone, and is not the bone of contention here. They are designed to be "brown-field" instructions, that is, fit into the unimplemented holes in the current spec. The reason the spec is going to split is not them, but the fact that Qualcomm also wants to remove the C extension, and put something else in the encoding space it frees.
  - Pet_Ant 3y ago
    Hmm, that seems like a mistake because C allows for instruction compression with low cost to decode that is perfect for embedded use which is a big part of the RISC-V usage now. That said, if they implemented C, and then had their replacement toggleable with a CSR that would still be backwards (albeit not forwards) compatible so that'd only be an issue if Qualcomm RISC-V binaries become dominant, but I don't think binaries are gonna be that dominant outside of firmware going forward, and any that are will be from vendors that will multi-target.
    - phkahler 3y ago
      >> Hmm, that seems like a mistake because C allows for instruction compression with low cost to decode that is perfect for embedded use which is a big part of the RISC-V usage now. It may be low cost to decode a compressed instruction, but having them means regular 32-bit instructions can cross cache lines and page boundaries. My own thought is that there should be a "next" version or RISC-VI that is mostly assembler-level compatible but changes all the instruction encodings to be more sane. What that means exactly is still a bit fuzzy, but I am a fan of immediate data being stored after the opcode.
      - __s 3y ago
        yes, was curious why compression format didn't require 1. non compressed instructions are always 4 byte aligned (pad a 2 byte NOP if necessary, or use uncompressed 4 byte instruction to fix sizing) 2. jump targets are always 4 byte aligned (which exists without C, but C relaxes) This avoids cache line issues & avoids jumps landing inside an instruction. Can consider each 2 compressed instructions as a single 4 byte instruction Bit redundant to encode C prefix twice, so there's room to make use of that (take up less encoding space at least by having prefix be 2x as long), but not important
Tuna-Fish 3y ago
The solution to this is not to split, but just follow Qualcomm. Their vision for the future of the ISA is simply much better than SiFive's. Right now, most devices on the market do not support the C extension, and any code that tries to be compatible does not use it. Qualcomm wants to remove it because it is actively harmful for fast implementations, and burns 75% of the entire encoding space, which is already extremely tight. SiFive really wants to keep it. The solution to fragmentation is to just disable the C extension everywhere, but SiFive doesn't want to hear that.
- camel-cdr 3y ago
  > most devices on the market do not support the C extension Name one that doesn't, it's exactly the opposite (for 64-bit).
  - GeorgeTirebiter 3y ago
    Maybe you've found the solution: RV32 must have the C extension. RV64 and RV128 must NOT have the C extension. Problem solved?
    - camel-cdr 3y ago
      No I meant, that for 64-bit CPUs virtually every available one supports the C extension.
- sitkack 3y ago
  > Right now, most devices on the market do not support the C extension This is not true and easily verifiable. The C extension is defacto required, the only cores that don't support it are special purpose soft cores. C extension in the smallest IP available core https://github.com/olofk/serv?tab=readme-ov-file https://github.com/olofk/serv?tab=readme-ov-file Supports M and C extensions https://github.com/YosysHQ/picorv32 https://github.com/YosysHQ/picorv32 Another sized optimized core with C extension support https://github.com/lowrisc/ibex https://github.com/lowrisc/ibex C extension in the 10 cent microcontroller https://www.wch-ic.com/products/CH32V003.html https://www.wch-ic.com/products/CH32V003.html This one should get your goat, it implements as much as it can using only compressed instructions https://github.com/gsmecher/minimax https://github.com/gsmecher/minimax

Dylan16807 3y ago

> to be more arm64ish I have a hard time picturing what this means. There's so much flexibility in implementing a core; what would they want to change in the ISA to make them like it better in a non-negligible way?

fidotron 3y ago
Prior discussion includes https://news.ycombinator.com/item?id=37996820 https://news.ycombinator.com/item?id=37996820
Tuna-Fish 3y ago
Mainly, richer addressing modes. SiFive designed RISC-V to have braindead-level simple addressing modes, with the idea that you use 2-4 normal alu ops to do addressing instead of a single op with a more complicated addressing mode. Then, to reduce the horrible impact this has on code size, they introduced the C extension that burns 75% of the encoding space of 32-bit instructions on 16-bit instructions, but this is still only a bandaid and a much weaker solution than having better addressing modes in the first place.
- camel-cdr 3y ago
  It's not as black and white as you portray it. Both sides of the argument agree that high-performance implementations are doable and not hindered much buy both, you can watch the debate in the profiles SIG zoom meetings. I think the real dispute was how the opcode space and code density will evolve when more and more extension will need to be added. Will more 32 opcode space and aligned 64 bit instructions but no 16 and no 48 bit instructions in the longterm be a better choice than fewer 32 bit instructions, but 16/48/64 bit instructions? Qualcomm is also currently involved in the Combined Instructions SIG, and proposed a few instructions in that vain: https://docs.google.com/spreadsheets/d/1dQYU7QQ-SnIoXp9vVvVjS6Jz9vGWhwmsdbEOF3JBwUg/edit#gid=0 https://docs.google.com/spreadsheets/d/1dQYU7QQ-SnIoXp9vVvVj.... Notice that these are currently very mild combined instructions, like BEQI, or CLO, which are unlikely to be cracked into uops compared to more complex addressing modes (e.g. apple silicon needs to crack pre/post increment load/stores). BTW, this article is actually about removing Qualcomm specific stuff from android, see: https://lists.riscv.org/g/sig-android/topic/105816077#msg389 https://lists.riscv.org/g/sig-android/topic/105816077#msg389