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Logik: Open-source FPGA toolchain by Zero ASIC
- UncleOxidant 3y agoIsn't it Yosys and VPR doing the heavy lifting here?
- adapteva 3y agoYes
- zachbee 3y agoThis doesn't appear to support any FPGAs other than their FPGA chiplet [1]. Also, like UncleOxidant said, the most complex parts of this toolchain are just existing open-source tools (Yosys and VPR). This seems like a useful toolchain for ZeroASIC customers who are using their hardware, but not for FPGA enthusiasts more broadly. [1]. https://www.zeroasic.com/chiplets/fpga https://www.zeroasic.com/chiplets/fpga
- sitzkrieg 3y agoyea this caught me too. that online digital twin is pretty slick tho
- hedgehog 3y agoI think it supports whatever SiliconCompiler supports (which is both FPGA and different ASIC flows) and the EBRICK example is showing how to put that design onto an ASIC or FPGA for testing. Edit: Here's the SiliconCompiler list: https://docs.siliconcompiler.com/en/stable/user_guide/introduction.html#supported-technologies https://docs.siliconcompiler.com/en/stable/user_guide/introd...
- cushychicken 3y agoCommoditize your complements, baby.
- adrian_b 3y agoEven so, it is very commendable for them to provide an open-source toolchain for their hardware, unlike the other vendors. At least for me, this is a strong argument for choosing their products, where appropriate.
- snvzz 3y agoWhat are the advantages of this? e.g. How does this compare to using a Makefile? (which is what I've been doing so far, and does not feel complex)
- adapteva 3y agoMakefiles can work for simple builds. Logik being Python based can do so much more: automated metrics gathering, conditional flows, parallel execution, error handling, dependency management
- marcodiego 3y agoI use to say this whenever I see anything related to FPGA: the FPGA world needs it's equivalent to Arduino. Before the Arduino, the world of microcontrollers was dominated by bad proprietary tools; the FPGA world suffers of the same illness today. We really need to fix this before FPGA's falls in the hands and hearts of any willing hobbyist.
- 0xcde4c3db 3y agoPeople have been working on it for years, but it's a lot of work when the chip vendor isn't helping to make it happen. At this point it's more akin to building reverse-engineered GPU drivers like Panfrost and Nouveau than a platform like Arduino (where AVR was well-documented by Atmel and avr-gcc already existed).
- sitkack 3y agoThe solution is to build our own FPGAs, fpgas are not more complex than any other ASIC, in fact more regular and simpler. There are multiple fpga fabric generators FABulous OpenFPGA PRGA Uranus All of which could lay down a fabric that could be programmed by OSS tools.
- qiqitori 3y agoLattice Semiconductor's iCE40 sort of qualifies, no? (Maybe getting a little old now?) Cheap and fully supported by an open-source toolchain and really easy to use. (Unless a GUI is needed.)
- londons_explore 3y agoIn computer programming, you can get say a ~10x speed improvement between writing bit twiddling code in python and hand writing SIMD assembly to do the same job. Is there a similar gaping gap between writing verilog for something, vs hand-designing the lookup tables and laying out the FPGA routing?
- sitkack 3y agoPython to SIMD is 1000x, to HDL it is 10k to 100k multiple. Python is 100x slower than native code. SIMD often gets you a 10x increase or more from native.
- nrclark 3y agoMost FPGAs have various kinds of primitives that can be instantiated manually in the middle of a larger Verilog design. Sometimes those primitives can be used to do things that are very hard to make the synthesizer create automatically. In general, the synthesizer will be better than you at anything lookup-table or flip-flop related. Ditto for simple primitives like shift-registers. But it probably doesn't know how to infer the more complicated primitives, and so those are usually done with the Verilog equivalent of inline assembly. For a few tight designs, I've given some hints to the the placer. These are things like grouping components together, or setting location constraints on a few key primitives. That kind of thing isn't too uncommon. I've never seen anybody try to route things manually though.
- adapteva 3y agoHaha, cool to see this on HN.:-) Yosys and vpr is clearly doing the heavy lifting here...the novelty here is the fact that an FPGA startup is giving public access to the fpga pre production and is opening the bit stream format. This hasn't really been done before.