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AMD announces the Spartan UltraScale+ FPGA family
- DrNosferatu 3y agoComparison to the one in MiSTer?
- shrubble 3y agoMiSTer is about 110K , this can go up to 218K. Probably this new FPGA is something like BGA package, since it has over 500 I/O pins. Also not available this year: "AMD Spartan UltraScale+ samples and evaluation kits are expected to be available for sampling and evaluation in the first half of 2025."
- stephen_g 3y agoThis isn't "a" new FPGA, there'll be like 50+ (or even hundreds of) SKUs, many will be various BGA/chip scale packages (with different numbers of pins available) but not necessarily all of them. The Spartan line, being the lowest level of Xilinx's FPGAs, have traditionally had a few versions in TQFP packages. I wouldn't be incredibly surprised if they did with this new version (although it's probably less and less likely with each generation).
- duskwuff 3y agoThere weren't any TQFP packages in 7-series either, and I don't expect that to change for US+. Even Spartan-6 only had that package for their smallest parts (XC6SLX4/LX9).
- YakBizzarro 3y agoInteresting product. It seems they ported some feature from the Versal family, like the hard LPDDR controller and the new XP5IO, so not just a cut down version of the bigger Artix
- ThaRedah 3y agoKeen to see how this impacts emulator development.
- jeff-davis 3y agoWhat are some killer apps for FPGAs? What major products do they enable?
- dragonelite 3y agoGiven the importance of Storage and Networking when working with big data for LLM. Having storage and network code in FPGA might be useful..
- harry8 3y agoStuff with a lot of simultaneous i/o that needs to be processed simultaneously, is one answer. https://www.intel.com/content/www/us/en/healthcare-it/products/programmable/overview.html https://www.intel.com/content/www/us/en/healthcare-it/produc...
- mynameisnoone 3y ago[flagged]
- dailykoder 3y agoThey enable a lot of crazy defence products. A well known german product for example is the Iris-T from Diehl Defence. Highly accurate and exceptional engineering. But I guess FPGAs are in most defence products nowadays. I think the biggest reason is that you can build/verify your own hardware without having to go through the expensive ASIC manufacturing Edit: I just realized that these are some literal killer apps. That wasn't even intentional, lol.
- bayindirh 3y ago> But I guess FPGAs are in most defence products nowadays. Yes. > I think the biggest reason is that you can build/verify your own hardware without having to go through the expensive ASIC manufacturing. Plus, you don't give out your secrets to fabs, too. Design, verify, launch, discard, without the need for signing an NDA.
- jeff-davis 3y ago
- sylware 3y agoI wonder what is the hardware programming interface. Something "horribly" simple I hope and suppose (memory mapped command ring buffers and dma buffers?) Then quickly getting up and running a shmol RV64 core... and I guess this is hacker paradise.
- hobo_mark 3y agoAn FPGA is a blank slate, more so than a CPU is, the programming interface is whatever the user wants to implement (including ring buffers and DMA or whatever).
- delfinom 3y agoIn FPGAs you are literally programming the enablement of individual logic gates. That's it. There is no DMA or command ring, you have to implement it yourself. The FPGA bit code itself is extremely propertiary to each vendor as the nature of controlling all the logic sauces is all secret sauce. So you have to use the vendors tooling.
- sylware 3y agoIf we have to go thru a closed source or brain damaged hardware programming interface, this is a loss for us.
- EraYaN 3y agoIt has basically always been this way. Xilinx wasn't different before this announcement. Altera wasn't and isn't either. Some of the smaller lattice designs are a bit more open, but are a different market segment. You will use Vivado and you will like it!
- 15155 3y ago> I wonder what is the hardware programming interface. Vivado > Then quickly getting up and running a shmol RV64 core... and I guess this is hacker paradise. https://github.com/SpinalHDL/NaxRiscv https://github.com/SpinalHDL/NaxRiscv
- willis936 3y agoNo hard core is a bummer. I want to see the first party SOM.
- dfox 3y agoYou mean something like this: https://www.amd.com/en/products/system-on-modules/kria.html https://www.amd.com/en/products/system-on-modules/kria.html Spartan is the glue-logic family for applications that either do not require any kind of CPU core at all or where some simple soft-core (MicorBlaze, x51, hand crafted state machine...) suffices.
- willis936 3y agoYes I do mean the Kria line, but one for this new Spartan Ultrascale+. I already buy packaged versions of $30 FPGAs because it alleviates most of the integration effort.
- deleted 3y ago[deleted]
- FirmwareBurner 3y agoWhy? They have a different line for that. Not worth wasting expensive silicone die area for something a lot of customers or projects won't need.
- willis936 3y agoBecause a hard core is much smaller and efficient than a soft core. Any small edge application you want to run embedded code on (which I argue is most all) will now need an external hard core or use a lot of precious PL resources and power for a soft core.
- FirmwareBurner 3y agoThey already sell other models with hard cores for those who need that since not all applications do.
- anonymousDan 3y agoShame it is only PCI-e Gen 4.
- Aromasin 3y agoYou don't seem to get PCIe Gen 5 outside of the top-end devices it seems. Agilex 7 has it on the Intel side with the R-Tile devices (including a hard CXL IP too which is lovely), but their recently announced Agilex 5 (the UltraScale+ competitor) only host PCIe 4.0 x8. I guess it takes up too much in terms of resources to double the throughput on a low-power device.
- mukundmr 3y agoFrom the article "AMD Spartan UltraScale+ samples and evaluation kits are expected to be available for sampling and evaluation in the first half of 2025." For hardware products, what is the point of making these announcements a year in advance? Are they available for select partners before 2025?
- guepe 3y agoYes they are.
- Aurornis 3y agoIf you know your product needs these features you can do early prototyping and development on similar or higher end platforms and then switch to this new platform when it becomes available. Having knowledge of upcoming parts is important in hardware engineering for planning purposes.
- morphle 3y agoWhen you need to decide on what FPGA line you are going to base your products on, you certainly want to know years in advance what new models will obsolete your FPGA products. However, you don't just want to know their specifications but also their price.
- DannyBee 3y agoThis is kinda true. But the flip side is most of them tell you ahead of time whether something is recommended for new designs, and how long they will guarantee production for. Which is much more important. In this day and age with FPGA companies being merged and spun out left and right, i doubt anyone relies on the future line announcements this second. In more normal times I agree you want to know if you are going down a dead end path.
- aylons 3y agoOh, yes. Hardware products and projects, specially those complex enough to need an FPGA, will usually have a long development pipeline and even one year seems pretty short. And you can very often prototype with either an overpowered development board or you own prototype board with another FPGA, and then downsize appropriately as the project advances. Most importantly, if you know there will be a viable version in a year, you can postpone the final decision and Xilinx get to avoid having you choosing Altera now if it's possible that their new offering will match your project.
- smallmancontrov 3y ago> Transceivers – Up to 8 GTH transceivers supporting up to 16.3 Gb/s Hey, the Spartan line is useful again!
- morphle 3y agoFinally, I waited years for this. I could only use the Kitex line. Big question is will these Spartan Ultrascale+ with tranceivers and PCIe 4.0 be cheaper or more expensive?
- amirhirsch 3y agoThey have strong competition from Lattice and I really thought they had ceded the low-end to them already. For the PCIe chips you can figure out where the pricing must fall for a certain feature set, but I'd be surprised if the cheapest PCIe 4.0 part in the Spartan US+ family is under $500. Consider the Lattice Avant-X series as competitive reference: https://www.mouser.com/c/semiconductors/programmable-logic-ics/fpga-field-programmable-gate-array/?q=AT-X&m=Lattice&tradename=Avant&sort=pricing https://www.mouser.com/c/semiconductors/programmable-logic-i...
- morphle 3y agoStrong competition from Lattice? I might be missing something, but AFAIK Lattice certuspro-nx FPGA's are more expesive and so is the synthesis software.
- DannyBee 3y agoThey already supported this line rate though, for years? What am i missing? (IE It's still only pcie gen3, and this announcement doesn't change that)
- smallmancontrov 3y agoSpartan 6 had transceivers. Spartan 7 dropped them. Boo. Spartan UltraScale+ brings them back. Hooray! (Though to morphie's point we should probably hold the champagne until we see pricing.) Also, it looks like PCIe Gen 4. The bitrate is enough and the page says Gen4x8. Is there something I'm missing?
- MegaDeKay 3y agoIt would be incredible if AMD made some open source moves with their FPGAs as they did with their GPUs. That would allow open source tools like Yosys and nextptr to work with them easily vs. the painstaking reverse engineering efforts this now requires. Xilinx Vivado is a massive beast of a thing. https://github.com/YosysHQ https://github.com/YosysHQ
- deleted 3y ago[deleted]
- kjs3 3y agoI think the issue is there are different market drivers at play. GPUs are more 'visible' than FPGAs to consumers; there's probably a couple of orders of magnitude more people pushing for open source/hackable drivers for GPUs than FPGAs (at least today). So AMD doesn't feel the pressure in the FPGA market, and it's 'easier' to maintain the status quo. I suspect we'll have to wait for a use case where somewhere near as many average users are actually thinking about their FPGA vendor as they do about their GPU vendor before things will change. Maybe an AI/ML application?
- vrinsd 3y agoThis "announcement" is basically a no-op. It's very likely not a new device but taking something like an Artix and just re-branding it and then limiting access to device features via software(Vivado). The same was done for 'Spartan-7' -- it was NOT a new device, just an existing design where they removed the SERDES block. What made Spartan-6 unique was in addition to having transcievers was the hardened DDR memory controller. If you read this announcement, DDR support is done via 'soft' memory controller, which chews up a lot of resources and makes meeting timing frustrating, forcing use of Xilinx's MIG IP.