4 ms·
What tool can you advise me to find the best combination of dividers and multipliers in PLL clocks and dividers in the UART and SPI peripherals so that the devi
by dsab 3y ago
What tool can you advise me to find the best combination of dividers and multipliers in PLL clocks and dividers in the UART and SPI peripherals so that the deviation from the assumed baudrate is as small as possible and that the dividers meet a number of constraints, including e.g. those from the chip errata which says that one PLL must be 2 times faster than the other?
- fedegiova 3y agoWrite a half page long python script that iterate all combinations , it won't take long, and you have to do that only once
- segfaultbuserr 3y ago"When in doubt, use brute force." - Ken Thompson
- amelius 3y agoBasically the underlying principle of Prolog.
- imtringued 3y agoTry optlang. It mostly does ILP/LP though.
- gavinray 3y agoI've had good experiences with OptaPlanner: https://www.optaplanner.org/ https://www.optaplanner.org/
- rsaxvc 3y agoExcel. Conditionally format based on constrain violations and difference from target baudrate. Brute force and scroll.