4 ms·

It wasn't that long ago that I could package silicon with a little quartz window. Anyone who remembers old-skool EPROMS will know what I mean. When doing my V

It wasn't that long ago that I could package silicon with a little quartz window. Anyone who remembers old-skool EPROMS will know what I mean. When doing my VLSI course at UCL in the 1980s we all had to make a "chip". Mine was a 16 bit counter with ripple adder and accumulator. And we had them fabbed (yes probably unbelievable in this day and age) and had to test them on the lab bench! BTW I'm not talking about FPGA here. We actually had a class visit to the fab-plant and put on bunny suits to go into a level-3 clean area and look at our UV masks in the projector room. So, obviously to save money, all the class had a little bit of silicon real-estate and some shared tristate registers that we could access our design through with our own address space. Now my point is; that when the chips were delivered we were all super excited. We looked at our silicon through a high power bench microscope. Everyone had signed their name (initials) in silicon next to their plot on the die. I remember marvelling at the smallest writing I had ever done in my life! So, here's part of how you make semi-secure hardware. Hardware you can actually look at using a simple lab microscope, no need for x-rays etc. Just sample randomly from the wafers and have those packaged in quartz, while 99% of the rest are normally packaged in opaque resin/ceramic. Make the randomly sampled wafers available for public inspection.

rcxdude 3y ago
Even on older nodes this is harder than you would expect, because you can't see past the first layer with visible light. There is more recent blog post fromt he same author looking at using infrared microscopy to do some verification of chips though (you can't see the low level details alas, but at least it makes it harder to hide something when it has to blend in with what the chip is supposed to look like)
- gnramires 3y ago
  Even if your process is destructive, you can still use statistics to get a probabilistic verification. For example, buy 10 chips, verify 9 randomly. If all are clean, then there's 90% confidence your chip is clean as well. More realistically, you would collect samples (a certain %) from a large batch to check none is compromised, and then take corrective measures to secure your supply chain. This kind of technique might be significant in highly sensitive applications like electronic voting.
- jacquesm 3y ago
  The fairly obvious solution here is to stop integration at the point where a truth table can be made of a single chip. That would allow you to exhaustively verify your design. It would run slower but there is no way that I can imagine that would allow a lowly logic circuit to suddenly become something else and both know it's place in the whole circuit, have access to an interesting datastream and be able to exfiltrate all at the same time. But once circuitry gets more complicated and chips become more integrated you can do just that because the only thing that would need to change is the contents of one single chip. There was a big scare around small components used to insert new code into target machinery: https://www.bloomberg.com/news/features/2018-10-04/the-big-hack-how-china-used-a-tiny-chip-to-infiltrate-america-s-top-companies https://www.bloomberg.com/news/features/2018-10-04/the-big-h... But that - if true - mostly hinged on being able to dynamically alter the software loaded into a high level design where the purpose, wiring diagram and target were intimately known to the attackers, all they had to do was engage in camouflaging their part as something innocent, any kind of component level audit would show that this part - which apparently wasn't on the circuit diagram in the first place - performed to its normal specifications. Initially I was quite skeptical but then a while later this appeared: https://www.schneier.com/blog/archives/2021/02/chinese-supply-chain-attack-on-computer-systems.html https://www.schneier.com/blog/archives/2021/02/chinese-suppl... And with this file as background: https://www.eff.org/files/2014/01/06/20131230-appelbaum-nsa_ant_catalog.pdf https://www.eff.org/files/2014/01/06/20131230-appelbaum-nsa_... That makes the attack sound more plausible. The practical upshot is that if you outsource your fabrication to an unknown third party that you can never be sure what you get unless your skills are orders of magnitude better than theirs. This goes for normal hardware and probably for high value targets and networking components you will have to be extra careful. But I'd be just as careful with for instance large battery packs or things that can be turned on or off remotely. (But that's getting away from component level bad stuff and into the realm of 'normal' attack vectors into embedded hardware.)
  - nonrandomstring 3y ago
    Terrifying on the same level as Ken Thompson's "On trusting trust". In theory even a capacitor could be listening for a serial activation code and then go short or open circuit to modulate a new signal onto a wire. Where the hell does that leave us?
xw3098 3y ago
In many Universities one can still have their design manufactured. For example: https://explorecourses.stanford.edu/search?view=catalog&filter-coursestatus-Active=on&page=0&q=EE372 https://explorecourses.stanford.edu/search?view=catalog&filt... That’s just the one I’m familiar with. I know there are others. Mostly they use MPWs now though so one can’t visit the site. But the price is pretty low. One can get ~100 qty 10 mm^2 packaged parts for maybe $20K
- jazzyjackson 3y ago
  ECE building at UIUC has a "nano fab lab" that can be viewed through orange tinted plate glass in the lobby. https://grainger.illinois.edu/news/stories/composing-the-future https://grainger.illinois.edu/news/stories/composing-the-fut...
Animats 3y ago
Famously, when Jim Clark, founder of Silicon Graphics, took such a course, his project was a 4x4 multiply/adder, the core of a GPU.
- dekhn 3y ago
  I mean, his Stanford work (when he was a professor) was the basis for the series of graphics engines SGI released. It's interesting to think about the Times Before, when people didn't appreciate graphics acceleration or matrix calculations nearly as much as we do today. https://graphics.stanford.edu/courses/cs148-10-summer/docs/1982--clark--geometry_engine.pdf https://graphics.stanford.edu/courses/cs148-10-summer/docs/1... https://www.computer.org/publications/tech-news/chasing-pixels/geometry-engine https://www.computer.org/publications/tech-news/chasing-pixe... http://bitsavers.trailing-edge.com/pdf/sgi/iris/geometry_engine/Clark_-_GeomEng.L2Q80.pdf http://bitsavers.trailing-edge.com/pdf/sgi/iris/geometry_eng...
  - Animats 3y ago
    What to do was understood as early as the Evans and Sutherland Line Drawing System 1 in the early 1970s, which had 4x4 transform hardware. But the GPU was a cabinet the size of a mainframe CPU. There were a series of mainframe-sized GPUs from E&S. Jim Clark worked for E&S. Affordability was a few decades ahead.
abdullahkhalids 3y ago
If you sign up for TinyTapeout [1], you can design a small digital circuit and have it manufactured on actual silicon for about a 100 dollars. It will be the same as your scenario, where everyone gets a tiny patch on the larger chip. You get the chip at the end. [1] https://tinytapeout.com/ https://tinytapeout.com/ No affiliation, but participated in an earlier run.
creer 3y ago
The same MOSIS still operates. https://themosisservice.com/ https://themosisservice.com/
wslh 3y ago
Impressing. Could we produce simpler chips at home with the current technology?
- jazzyjackson 3y ago
  see here: http://sam.zeloof.xyz/second-ic/ http://sam.zeloof.xyz/second-ic/
salawat 3y ago
...Which just means you submit two designs. One for the chip people see, one for the chip people can't. If you don't think that wouldn't be done, you've got a bit more living to do.
marcosdumay 3y ago
Just to add a point of view, most of what we do with computers is easily verifiable (or of no concern). So the part that actually needs to be trustworthy is relatively small. But I have no proposal of architecture that includes an external verification processor.

rcxdude 3y ago

Even on older nodes this is harder than you would expect, because you can't see past the first layer with visible light. There is more recent blog post fromt he same author looking at using infrared microscopy to do some verification of chips though (you can't see the low level details alas, but at least it makes it harder to hide something when it has to blend in with what the chip is supposed to look like)

gnramires 3y ago
Even if your process is destructive, you can still use statistics to get a probabilistic verification. For example, buy 10 chips, verify 9 randomly. If all are clean, then there's 90% confidence your chip is clean as well. More realistically, you would collect samples (a certain %) from a large batch to check none is compromised, and then take corrective measures to secure your supply chain. This kind of technique might be significant in highly sensitive applications like electronic voting.
jacquesm 3y ago
The fairly obvious solution here is to stop integration at the point where a truth table can be made of a single chip. That would allow you to exhaustively verify your design. It would run slower but there is no way that I can imagine that would allow a lowly logic circuit to suddenly become something else and both know it's place in the whole circuit, have access to an interesting datastream and be able to exfiltrate all at the same time. But once circuitry gets more complicated and chips become more integrated you can do just that because the only thing that would need to change is the contents of one single chip. There was a big scare around small components used to insert new code into target machinery: https://www.bloomberg.com/news/features/2018-10-04/the-big-hack-how-china-used-a-tiny-chip-to-infiltrate-america-s-top-companies https://www.bloomberg.com/news/features/2018-10-04/the-big-h... But that - if true - mostly hinged on being able to dynamically alter the software loaded into a high level design where the purpose, wiring diagram and target were intimately known to the attackers, all they had to do was engage in camouflaging their part as something innocent, any kind of component level audit would show that this part - which apparently wasn't on the circuit diagram in the first place - performed to its normal specifications. Initially I was quite skeptical but then a while later this appeared: https://www.schneier.com/blog/archives/2021/02/chinese-supply-chain-attack-on-computer-systems.html https://www.schneier.com/blog/archives/2021/02/chinese-suppl... And with this file as background: https://www.eff.org/files/2014/01/06/20131230-appelbaum-nsa_ant_catalog.pdf https://www.eff.org/files/2014/01/06/20131230-appelbaum-nsa_... That makes the attack sound more plausible. The practical upshot is that if you outsource your fabrication to an unknown third party that you can never be sure what you get unless your skills are orders of magnitude better than theirs. This goes for normal hardware and probably for high value targets and networking components you will have to be extra careful. But I'd be just as careful with for instance large battery packs or things that can be turned on or off remotely. (But that's getting away from component level bad stuff and into the realm of 'normal' attack vectors into embedded hardware.)
- nonrandomstring 3y ago
  Terrifying on the same level as Ken Thompson's "On trusting trust". In theory even a capacitor could be listening for a serial activation code and then go short or open circuit to modulate a new signal onto a wire. Where the hell does that leave us?

xw3098 3y ago

In many Universities one can still have their design manufactured. For example: https://explorecourses.stanford.edu/search?view=catalog&filter-coursestatus-Active=on&page=0&q=EE372 https://explorecourses.stanford.edu/search?view=catalog&filt... That’s just the one I’m familiar with. I know there are others. Mostly they use MPWs now though so one can’t visit the site. But the price is pretty low. One can get ~100 qty 10 mm^2 packaged parts for maybe $20K

jazzyjackson 3y ago
ECE building at UIUC has a "nano fab lab" that can be viewed through orange tinted plate glass in the lobby. https://grainger.illinois.edu/news/stories/composing-the-future https://grainger.illinois.edu/news/stories/composing-the-fut...

Animats 3y ago

Famously, when Jim Clark, founder of Silicon Graphics, took such a course, his project was a 4x4 multiply/adder, the core of a GPU.

dekhn 3y ago
I mean, his Stanford work (when he was a professor) was the basis for the series of graphics engines SGI released. It's interesting to think about the Times Before, when people didn't appreciate graphics acceleration or matrix calculations nearly as much as we do today. https://graphics.stanford.edu/courses/cs148-10-summer/docs/1982--clark--geometry_engine.pdf https://graphics.stanford.edu/courses/cs148-10-summer/docs/1... https://www.computer.org/publications/tech-news/chasing-pixels/geometry-engine https://www.computer.org/publications/tech-news/chasing-pixe... http://bitsavers.trailing-edge.com/pdf/sgi/iris/geometry_engine/Clark_-_GeomEng.L2Q80.pdf http://bitsavers.trailing-edge.com/pdf/sgi/iris/geometry_eng...
- Animats 3y ago
  What to do was understood as early as the Evans and Sutherland Line Drawing System 1 in the early 1970s, which had 4x4 transform hardware. But the GPU was a cabinet the size of a mainframe CPU. There were a series of mainframe-sized GPUs from E&S. Jim Clark worked for E&S. Affordability was a few decades ahead.

abdullahkhalids 3y ago

If you sign up for TinyTapeout [1], you can design a small digital circuit and have it manufactured on actual silicon for about a 100 dollars. It will be the same as your scenario, where everyone gets a tiny patch on the larger chip. You get the chip at the end. [1] https://tinytapeout.com/ https://tinytapeout.com/ No affiliation, but participated in an earlier run.

creer 3y ago

The same MOSIS still operates. https://themosisservice.com/ https://themosisservice.com/

wslh 3y ago

Impressing. Could we produce simpler chips at home with the current technology?

jazzyjackson 3y ago
see here: http://sam.zeloof.xyz/second-ic/ http://sam.zeloof.xyz/second-ic/

salawat 3y ago

...Which just means you submit two designs. One for the chip people see, one for the chip people can't. If you don't think that wouldn't be done, you've got a bit more living to do.

marcosdumay 3y ago

Just to add a point of view, most of what we do with computers is easily verifiable (or of no concern). So the part that actually needs to be trustworthy is relatively small. But I have no proposal of architecture that includes an external verification processor.