10 ms·

SiFive’s P870 Takes RISC-V Further

143 points by zdw 3y ago

OhMeadhbh 3y ago
I'm bullish on RISC-V, but sort of bearish on SiFive. The last several systems I've used have been StarFive systems (which is distinct from SiFive.) They (SiFive) seem to be more of a custom IP shop, where you go when you want to spin some custom silicon but not pay ARM. But now that we've broken with China re: chip production, is there anyone on this side of the pacific I can get catalog parts from? So... their cores are great, but if I'm only going to see them if I write a very large check to SiFive, they're sort of irrelevant to my world. I would love to have SiFive IP that doesn't use Rocket/Scala/Chisel and does produce catalog parts. That could be just me. I enjoy getting my hands dirty.
- photonbeam 3y ago
  You normally only see ARM when you cut a big check too, they sell IP that others get fab’d
  - OhMeadhbh 3y ago
    Well... our ARM cores use more standard tooling. I sort of detest System Verilog, but I detest it a lot less than Rocket/Chisel. And as annoying as it is to write a big check to ARM, at least you can hire people who know how to use your IP. It probably wasn't obvious from my earlier comment, but I was comparing SiFive to ARM and then I was comparing SiFive with other RISC-V IP vendors (and open source projects.)
- fidotron 3y ago
  I agree with this, and suspect that if SiFive did get big enough they would start creating patented extensions as a defensive strategy. Personally I'm more curious about RISC-V in tiny microcontrollers, and were I guiding semiconductor strategy I'd be way more concerned about ability to build embedded systems than GPU farms. The ecosystem to do the former can evolve into the latter, but skipping to the end is just a route to burn absolutely billions.
  - OhMeadhbh 3y ago
    FWIW, after listening to Chuck Peddle's CHM Oral History interview, I sort of realized I didn't need the ARM ecosystem and just designed my own 6-bit microcontroller. Granted, I'm only doing some very simple control applications and fabbing at 800nm, so it's not going to be competing with an i7 or an A72 anytime soon. IIRC, the RISC-V spec includes an "embedded profile" that specifies a CPU with 16 32-bit registers, so that should make RV32 even smaller than it would be otherwise. SiFive designed a dog-simple 2-stage pipeline 32 bit core that could even run without I-cache. I mean, it's not a speed demon, but it was implementable in many fewer gates than their earlier E cores. I worked at SiFive for a year and couldn't make sense of their product strategy. But maybe that's a me problem and not a SiFive problem. I really do sort of wonder what they're doing with 175m in Series F funding. Where do you go from there?
    - photonbeam 3y ago
      Presumably lots of runway for salaries until next funding round or exit event
      - OhMeadhbh 3y ago
        Intel publicly walked away from a $2B offer for SiFive, which means that at least one large chip manufacturer does not believe their IP is worth more than $2B. I'm not sure if the Round F post-money valuation was made public, but if it's more than $2B, SiFive will need to have a solid story for why a potential buyer should pay more than what Intel didn't want to pay. And if they're going to IPO, it would be helpful to have a reference customer for newer designs which seem to be on par with ARM offerings from four years ago. It's certainly not impossible, but it seems a tough row to hoe. But the cool part of this is that the ISA and many supporting packages (rocket, boom, etc.) are "open" and "free as in beer." Even if SiFive did fail, an IP investment in RISC-V would not necessarily have been a bad move. Which is why I said I'm fairly bullish on RISC-V (cause even if SiFive fails, customers existing investment in the ISA is not lost) but bearish on SiFive (because I fear their existing valuation may be too inflated.) I'm not trying to tell anyone their SiFive baby is ugly. I'm not saying designing a RISC-V solution is a bad move. I'm just saying from my perspective, with incomplete information about what's going on inside SiFive, it looks like they have a difficult road ahead. I would POSITIVELY WELCOME any information regarding reference customers or catalog parts which might imply there's a large customer who's signed on the dotted line to pay SiFive a royalty for using their designs. Full disclosure: I own no SIFIVE stock (or options) nor do I own stock in any company that competes in the RISC-V design space (Esperanto, Andes, Sandisk/WD, etc.) I still have stock in TXN though, but I haven't heard that they're deep in RISC-V. I am a former employee of SiFive, but was not employed in a management position; don't take my comments as being based on "inside information."
- rwmj 3y ago
  They seem to be positioning themselves as the "RISC-V Arm" equivalent. Of course there are significant differences, like they don't completely control the architecture (as Arm does). But Arm have made a decent business out of it, so SiFive should be able to do the same. By the way StarFive were SiFive China until SiFive divested them (the split was a bit acrimonious).
  - qwytw 3y ago
    > But Arm have made a decent business ARM is making peanuts compared pretty much all the companies that actually make high-end chips. Their IP seems to be worth much more than the business.
    - rwmj 3y ago
      Just because Arm isn't huge, it's still not nothing. They're about to go into a floatation to try to raise $50-55 billion, which is not too shabby! (Even if it's down from the original target of over $60b).
      - qwytw 3y ago
        True (assuming the stock price doesen't crash immediately after the IPO) but still it's not really justifiable based on their current financial figures or future growth prospects. I'm not even sure what the valuation this valuation might even be based on (which admittedly applies to a bunch of other companies which actually end up doing quite well). They might conceivably be worth 100 P/E as an acquisition but an IPO would only make it less likely? $50-55 billion would mean that ARM is more overvalued than Nvidia and Nvidia actually has a realistic chance to grow into that valuation.
      - brucehoult 3y ago
        "Try" is doing a lot there. I can't see how Arm is even worth the $32 billion SoftBank paid for them now. RISC-V didn't exist outside of Berkeley in 2016 when SoftBank bought Arm, but now it's becoming a serious rival and especially a serious limitation on how much Arm can raise prices. Arm have around 2.7 billion in annual sales with $500m or $600m of profit. That makes $32b a P/E ratio of 50 to 60, and $50b a P/E ratio of 80 to 100. In simple terms, if you pay $50 billion to buy Arm, and they make the same profit every year as they are making now, it will take 80 to 100 years for you to make your investment back. It's like putting your money into a bank paying 1% interest, but a lot riskier. Such P/E ratios can only be justified by the company and its profits growing rapidly. Arm's revenue actually fell 1% from 2022 to 2023. The last four years have been roughly 2.0, 2.7, 2.75, 2.7. Is that a peak, and it's only downhill from now on, because of RISC-V (or otherwise). Or will they start to grow again? Either way, it sure doesn't look like the very high annual growth rate needed to justify a price of $30b let alone $50b.
- ChuckMcM 3y ago
  The ugly truth though is that "catalog parts" carry with it a whole boatload of overhead in the form of sockets/memory infrastructure/voltage regulators/cooling standards etc. The current "big money" is in being the core that gets integrated into a phone or tablet. It makes me sad too as this is a pretty spiffy micro-architecture to play around with.
  - OhMeadhbh 3y ago
    Oh hey Chuck! Yes. That's where the big money is. It seems their current top-of-the-line core is on par with an A72 or A77. I'm not sure how it stacks up against an Apple M1. My take on SiFive is it's at the point that it COULD compete, but they have to get more mind-share. If you're Samsung or Apple (or MediaTek or Allwinner or Rockchip or ...), you probably have experience with the ARM ecosystem and tools. Presumably you have a history with a business model and have factored in whatever royalties you're paying ARM into your cost of operations. It's a risk to set that aside and start using a different architecture, so you would want to have some quantifiable benefit before you ditched ARM for RISC-V. It seems to me that clearly elucidating that benefit to potential customers is an important part of this equation. SiFive's earlier designs seemed to have smaller PPA numbers, so that's nice. But they were for in-order execution w/o macro fusion or speculative branching, so they were a little closer to A53s in performance per watt. If you had a RV64 design with the performance per watt of an A77, but with a power/area budget 20% lower, that might have a REAL impact on yield and cost. That would be a thing to crow about. But that's not the type of crowing I see happening on the SiFive web page. I keep thinking a catalog part with maybe a pair of U-54s, a pair of 270s and a pair of 670s plus typical SoC peripherals would be a great way to introduce developers to what SiFive designs could do. They could give dev boards to Samsung, Zero, Google, LTE engineers who could tweak the existing android RISC-V android images to get an idea for performance and power use. Maybe they could sell Apple on the idea of acquihiring SiFive. Apple's never been skiddish about changing processor architectures or suppliers. So... to recap... I'm thinking catalog parts mostly as a vehicle to prove to potential customers your IP can be fabbed to meet their power / performance / yield / cost targets. And if I can buy a couple hundred of these boards for a different project, then I'm even happier.
- pama 3y ago
  Is there any good benchmark/comparison of the current risk-v boards for use in hobby projects?
  - brucehoult 3y ago
    If by "good" you mean "something that's probably about as good as Dhrystone or Coremark but a lot simpler and harder to game" then I've got a benchmark and quite a few results collected on various things over the last seven years here: https://hoult.org/primes.txt https://hoult.org/primes.txt
    - pama 3y ago
      Thanks. So some of these cpu, say VisionFive 2 U74, start to look interesting.
      - pama 3y ago
        Just noting for my own reference that the TH1520 is well within the interesting range.
    - OhMeadhbh 3y ago
      Though... RISC-V support in gnu c and clang have evolved significantly over the last 5 years. Did you re-run any of the tests with more recent compilers? When we were doing benchmarking 5 years ago, it seemed we got slightly better performance every month as Palmer integrated improvements into the gnu toolchain. There were at least a couple months there where we REALLY didn't want to publish benchmarks because we were expecting the numbers to be noticeably better in n days.
      - brucehoult 3y ago
        This is very straightforward code (which I wrote in 2016 before I'd even heard of RISC-V) that maps very cleanly and obviously to instructions and any gcc from the last 20 years will make essentially the same code. A large part of my goal when I wrote it was to make it far more impervious to compiler "improvements" and gaming that Dhrystone and Coremark -- and I think I succeeded very well. The RISC-V B extension's `sh2add` and friends make a small difference -- that's basically the 2.7% gap between the VisionFive 2 and the HiFive Unmatched. If I disable Zba on the VF2 then the times are just about identical.
- eigenform 3y ago
  I'm curious what your objections to Chisel are! (I don't really care for Scala either .. unless you mean that like, this somehow affects the way that IP is delivered to you as a customer? I thought you just get a big blob of verilog in the end, and I'm not sure how that'd affect you?)
  - OhMeadhbh 3y ago
    I'm not the worlds biggest fan of Verilog, but Verilog's semantics are relatively fixed. The interpretation of verilog has remained fairly stable for a decade at least. Chisel is in some ways still a work in progress. So if you want to use it, you have to keep track not only of Chisel productions specific to your design, but also the version of the boom or rocket generator you're using with it. Chisel was never at the center of our design flow, and none of the people I currently work with went to UCB. When we used the Rocket generator we were often "nervous" about whether the version we were using would interpret Chisel productions in the way in which it had previously. But yes... this led us to a working style where we tried very hard to avoid having to use rocket or boom generators. I didn't want to be in the business of maintaining RISC-V Verilog tools. At around the same time we realized RISC-V was overkill and built a very poorly designed Lisp DSL which output Verilog for a dog-simple 6-bit controller. Not an ideal solution to be sure, but it worked better for us than spending a couple years learning Rocket/Scala/Chisel. Nick Tredennick (who I believe was the main designer of the 68k) has a quote in his book "Logic Design: The Flowchart Method": The problem with many texts is that we lie about details. We are sloppy in areas that are not our primary concern. Academics are method fanatics. Practitioners are solution fanatics. In school, we glorify the methods and lie about the sophisticated problems we solved. In industry, we glorify the problems and lie about the sophisticated methods we used. Each side loses credibility the minute one side reads the other's literature. The academic knows that the practitioner's "method" is (ugh!) arbitrary, just as the practitioner knows the academic's "solution is (ugh!) not applicable. Because we oversell method and solution, it takes too long to figure out what really works. I don't want to say Rocket / Chisel / Firrtl is bad, but it always seemed to be more in support of a "process focused" methodology than the "solution oriented" focus I'm used to. If it works for you, I'm absolutely not going to tell you it's a bad idea to use it. It's just too much overhead for the small projects I work on. That being said... SiFive was working on CoC (theorum prover) extensions to validate designs using formal methods. THAT sounds fascinating, but I'm not sure how they would monetize it. [Edit: To recap, I don't have a problem with Rocket / Chisel / Firrtl per se, but they operate at a level I'm uncomfortable with and seem to be less stable than I would prefer. I completely understand this is not the case for many other people.]
- cinquemb 3y ago
  Makes me think that asia is gonna have this cheap compute available alot faster at the consumer level than anywhere else for at least the next 5-10 years.
camel-cdr 3y ago
> An insane programmer can set LMUL to a value higher than 1, making vector instructions address contiguous blocks of registers. I hope that most code won't use LMUL=1, but LMUL>=1 when possible, otherwise we'd leave performance on the table. The only case I can currently fore see where using LMUL=1 and manually unrolling instead will likely be always beneficial is vrgather operations that don't need to cross between registers in a register group (e.g. byte swapping). > As with all new architectural features, we’ll have to wait and see how useful RISC-V’s LMUL will be. RVV without LMUL would be a lot worse, the entire extension is build around the LMUL concept and it's really nice to work with imo.
- dsharlet 3y ago
  > The only case I can currently fore see where using LMUL=1 and manually unrolling instead will likely be always beneficial is vrgather operations that don't need to cross between registers in a register group (e.g. byte swapping). What about algorithms where register pressure is an issue? I think the problem with LMUL is it assumes that you always want to unroll the innermost dimension (where the vector loads are stride 1). That's usually, the last dimension I try to unroll, if there are any registers left over. If there is any sharing of data across any other dimension in the algorithm, it's better to tile/unroll those first. Of course, for a simple algorithm, there will be registers left over. But I think more interesting algorithms will struggle on RVV if you must use LMUL > 1 for performance.
  - camel-cdr 3y ago
    > What about algorithms where register pressure is an issue Then you'll probably saturate the processor without using a larger LMUL, but I think many algorithms can work with LMUL=2, without running out of registers.
  - brucehoult 3y ago
    LMUL (and especially fractional LMUL) isn't for performance, it's for kernels with mixed-element sizes, to maximise the number of variables (and elements) you can keep in registers without spilling. Being able to use LMUL as a way to get the effect of unrolling and hide the pointer bumps and loop control on simple loops on narrow processors, without expanding the code, is just a bonus.
yuumei 3y ago
Just a warning to anyone thinking of using the sifive boards https://forums.sifive.com/t/unmatched-boot-issues/6236 https://forums.sifive.com/t/unmatched-boot-issues/6236
- deleted 3y ago
  [deleted]
- greggsy 3y ago
  This just suggests that one board has an undiagnosed issue? Is there some other insight I’m missing?
brucethemoose2 3y ago
Tenstorrent has an 8-wide RISC-V core available for licensing: https://tenstorrent.com/risc-v/ https://tenstorrent.com/risc-v/ ...But I am starting to get suspicious of Tenstorrent. Maybe they have some customers using their designs privately, but I never see any of their hardware used in public.
- brucehoult 3y ago
  Both Keller joining and announcing they were going to use RISC-V happened in 2021. Why on earth would you expect to already be falling over hardware in 2023? CPU core design takes a couple of years, getting to the first test chips a couple more, and then to mass production a couple more after that.
  - brucethemoose2 3y ago
    Indeed, but another company should've announced they are licensing and taping out products on the cores by now, right? If someone starts taping it out right now, the core will be long in the tooth by the time it comes out. I am also suspicious because their 12nm, 2021 Grayskull PCIe cards never materialized: > We’ll be selling Tenstorrent AI PCIe cards, workstations, and servers soon. Stay tuned for availability. https://tenstorrent.com/grayskull/ https://tenstorrent.com/grayskull/
    - snvzz 3y ago
      Soon. Stay tuned. (no concrete promise, thus not late)
ireallywantthat 3y ago
Sorry for my ignorance, but any idea when we can see Desktop Processors powered by RISC-V architecture? It would be breath of fresh air to see new architectures power the desktops.
- AlotOfReading 3y ago
  You can buy a RISCV SBC and run a Linux desktop on it today. It's just not competitive with x86 in performance or software support. The closest you'll get to that outside arm or x86 is Talos II stuff, which runs PowerNV.
- marcodiego 3y ago
  I remember this one: https://abopen.com/news/building-a-risc-v-pc/ https://abopen.com/news/building-a-risc-v-pc/ . Since it is from 2019, it is likely there have been some advancements. I also hope for a riscv desktop; it could even be ryf certifiable.
- crote 3y ago
  The HiFive Pro P550 should be available this summer, for a pretty desktop-like experience. Don't expect RISV-V to directly compete with Intel/AMD on the high end for at least another decade, though.
  - snvzz 3y ago
    >Don't expect RISV-V to directly compete with Intel/AMD on the high end for at least another decade Actually 2024. SiFive P870, Tenstorrent Ascalon, SOPHON SG2044, Ventana Veyron, and more.
    - rwmj 3y ago
      Rivos too ...
      - snvzz 3y ago
        Rivos hasn't announced anything. There's several other companies we know are working on processors but haven't announced a thing.
phkahler 3y ago
We still need a an open and free GPU to pair with this in a SoC.
- deleted 3y ago
  [deleted]
- marcodiego 3y ago
  Hantro and panfrost fill this gap. No blob is required afaik.
  - MobiusHorizons 3y ago
    While very cool, open source drivers for propriety a proprietary gpu design is not quite the same as open silicon or open gpu isa, which is what I think the parent was asking for.
- 0xDEF 3y ago
  This is not an open and free CPU. It just implements the open and free RISC-V instruction set. Judging by the SiFive business model they will in the future inevitably add proprietary extensions.
sylware 3y ago
We will need some sort of soft tablesheet in order to know how to write assembly to leverage instruction fusion in a best effort fashion. I wonder how many GHz this µArch would reach with TSMC 3nm.
- sylware 3y ago
  Come on, with ASML EUV-HighNA with the smallest feature set we can have.
synergy20 3y ago
SiFive is now a IP license shop I think? similar to Andes from Taiwan who also sells RISC-V cores. Difference is that SiFive is more on the desktop CPU while Andes is more on the embedded space. In the Machine Learning startup field, RISC-V is the most popular choice these days. RISC-V also becomes a national priority for China as far as I can tell, it won't surprise me the best RISC-V designs will be from there.
codedokode 3y ago
> A 32 entry iTLB helps cache virtual to physical address translations on the instruction side. Why are TLBs so small? Are they super expensive or what? With 32 entries TLB it can cover only 1 Mb of RAM if using legacy 4k pages.
- johndoe0815 3y ago
  Yes, TLBs are pretty expensive (in area and power) since they are associative memories. The virtual (non-offset) part of an address to be translated is compared to all TLB entries simultaneously to keep latencies down since the TLB is on the critical path from CPU to memory. Accordingly, you need one comparator (lots of XOR gates in a simple implementation) per TLB entry.

143 points by zdw 3y ago

I'm bullish on RISC-V, but sort of bearish on SiFive. The last several systems I've used have been StarFive systems (which is distinct from SiFive.) They (SiFive) seem to be more of a custom IP shop, where you go when you want to spin some custom silicon but not pay ARM. But now that we've broken with China re: chip production, is there anyone on this side of the pacific I can get catalog parts from? So... their cores are great, but if I'm only going to see them if I write a very large check to SiFive, they're sort of irrelevant to my world. I would love to have SiFive IP that doesn't use Rocket/Scala/Chisel and does produce catalog parts. That could be just me. I enjoy getting my hands dirty.

photonbeam 3y ago
You normally only see ARM when you cut a big check too, they sell IP that others get fab’d
- OhMeadhbh 3y ago
  Well... our ARM cores use more standard tooling. I sort of detest System Verilog, but I detest it a lot less than Rocket/Chisel. And as annoying as it is to write a big check to ARM, at least you can hire people who know how to use your IP. It probably wasn't obvious from my earlier comment, but I was comparing SiFive to ARM and then I was comparing SiFive with other RISC-V IP vendors (and open source projects.)
fidotron 3y ago
I agree with this, and suspect that if SiFive did get big enough they would start creating patented extensions as a defensive strategy. Personally I'm more curious about RISC-V in tiny microcontrollers, and were I guiding semiconductor strategy I'd be way more concerned about ability to build embedded systems than GPU farms. The ecosystem to do the former can evolve into the latter, but skipping to the end is just a route to burn absolutely billions.
- OhMeadhbh 3y ago
  FWIW, after listening to Chuck Peddle's CHM Oral History interview, I sort of realized I didn't need the ARM ecosystem and just designed my own 6-bit microcontroller. Granted, I'm only doing some very simple control applications and fabbing at 800nm, so it's not going to be competing with an i7 or an A72 anytime soon. IIRC, the RISC-V spec includes an "embedded profile" that specifies a CPU with 16 32-bit registers, so that should make RV32 even smaller than it would be otherwise. SiFive designed a dog-simple 2-stage pipeline 32 bit core that could even run without I-cache. I mean, it's not a speed demon, but it was implementable in many fewer gates than their earlier E cores. I worked at SiFive for a year and couldn't make sense of their product strategy. But maybe that's a me problem and not a SiFive problem. I really do sort of wonder what they're doing with 175m in Series F funding. Where do you go from there?
  - photonbeam 3y ago
    Presumably lots of runway for salaries until next funding round or exit event
    - OhMeadhbh 3y ago
      Intel publicly walked away from a $2B offer for SiFive, which means that at least one large chip manufacturer does not believe their IP is worth more than $2B. I'm not sure if the Round F post-money valuation was made public, but if it's more than $2B, SiFive will need to have a solid story for why a potential buyer should pay more than what Intel didn't want to pay. And if they're going to IPO, it would be helpful to have a reference customer for newer designs which seem to be on par with ARM offerings from four years ago. It's certainly not impossible, but it seems a tough row to hoe. But the cool part of this is that the ISA and many supporting packages (rocket, boom, etc.) are "open" and "free as in beer." Even if SiFive did fail, an IP investment in RISC-V would not necessarily have been a bad move. Which is why I said I'm fairly bullish on RISC-V (cause even if SiFive fails, customers existing investment in the ISA is not lost) but bearish on SiFive (because I fear their existing valuation may be too inflated.) I'm not trying to tell anyone their SiFive baby is ugly. I'm not saying designing a RISC-V solution is a bad move. I'm just saying from my perspective, with incomplete information about what's going on inside SiFive, it looks like they have a difficult road ahead. I would POSITIVELY WELCOME any information regarding reference customers or catalog parts which might imply there's a large customer who's signed on the dotted line to pay SiFive a royalty for using their designs. Full disclosure: I own no SIFIVE stock (or options) nor do I own stock in any company that competes in the RISC-V design space (Esperanto, Andes, Sandisk/WD, etc.) I still have stock in TXN though, but I haven't heard that they're deep in RISC-V. I am a former employee of SiFive, but was not employed in a management position; don't take my comments as being based on "inside information."
rwmj 3y ago
They seem to be positioning themselves as the "RISC-V Arm" equivalent. Of course there are significant differences, like they don't completely control the architecture (as Arm does). But Arm have made a decent business out of it, so SiFive should be able to do the same. By the way StarFive were SiFive China until SiFive divested them (the split was a bit acrimonious).
- qwytw 3y ago
  > But Arm have made a decent business ARM is making peanuts compared pretty much all the companies that actually make high-end chips. Their IP seems to be worth much more than the business.
  - rwmj 3y ago
    Just because Arm isn't huge, it's still not nothing. They're about to go into a floatation to try to raise $50-55 billion, which is not too shabby! (Even if it's down from the original target of over $60b).
    - qwytw 3y ago
      True (assuming the stock price doesen't crash immediately after the IPO) but still it's not really justifiable based on their current financial figures or future growth prospects. I'm not even sure what the valuation this valuation might even be based on (which admittedly applies to a bunch of other companies which actually end up doing quite well). They might conceivably be worth 100 P/E as an acquisition but an IPO would only make it less likely? $50-55 billion would mean that ARM is more overvalued than Nvidia and Nvidia actually has a realistic chance to grow into that valuation.
    - brucehoult 3y ago
      "Try" is doing a lot there. I can't see how Arm is even worth the $32 billion SoftBank paid for them now. RISC-V didn't exist outside of Berkeley in 2016 when SoftBank bought Arm, but now it's becoming a serious rival and especially a serious limitation on how much Arm can raise prices. Arm have around 2.7 billion in annual sales with $500m or $600m of profit. That makes $32b a P/E ratio of 50 to 60, and $50b a P/E ratio of 80 to 100. In simple terms, if you pay $50 billion to buy Arm, and they make the same profit every year as they are making now, it will take 80 to 100 years for you to make your investment back. It's like putting your money into a bank paying 1% interest, but a lot riskier. Such P/E ratios can only be justified by the company and its profits growing rapidly. Arm's revenue actually fell 1% from 2022 to 2023. The last four years have been roughly 2.0, 2.7, 2.75, 2.7. Is that a peak, and it's only downhill from now on, because of RISC-V (or otherwise). Or will they start to grow again? Either way, it sure doesn't look like the very high annual growth rate needed to justify a price of $30b let alone $50b.
ChuckMcM 3y ago
The ugly truth though is that "catalog parts" carry with it a whole boatload of overhead in the form of sockets/memory infrastructure/voltage regulators/cooling standards etc. The current "big money" is in being the core that gets integrated into a phone or tablet. It makes me sad too as this is a pretty spiffy micro-architecture to play around with.
- OhMeadhbh 3y ago
  Oh hey Chuck! Yes. That's where the big money is. It seems their current top-of-the-line core is on par with an A72 or A77. I'm not sure how it stacks up against an Apple M1. My take on SiFive is it's at the point that it COULD compete, but they have to get more mind-share. If you're Samsung or Apple (or MediaTek or Allwinner or Rockchip or ...), you probably have experience with the ARM ecosystem and tools. Presumably you have a history with a business model and have factored in whatever royalties you're paying ARM into your cost of operations. It's a risk to set that aside and start using a different architecture, so you would want to have some quantifiable benefit before you ditched ARM for RISC-V. It seems to me that clearly elucidating that benefit to potential customers is an important part of this equation. SiFive's earlier designs seemed to have smaller PPA numbers, so that's nice. But they were for in-order execution w/o macro fusion or speculative branching, so they were a little closer to A53s in performance per watt. If you had a RV64 design with the performance per watt of an A77, but with a power/area budget 20% lower, that might have a REAL impact on yield and cost. That would be a thing to crow about. But that's not the type of crowing I see happening on the SiFive web page. I keep thinking a catalog part with maybe a pair of U-54s, a pair of 270s and a pair of 670s plus typical SoC peripherals would be a great way to introduce developers to what SiFive designs could do. They could give dev boards to Samsung, Zero, Google, LTE engineers who could tweak the existing android RISC-V android images to get an idea for performance and power use. Maybe they could sell Apple on the idea of acquihiring SiFive. Apple's never been skiddish about changing processor architectures or suppliers. So... to recap... I'm thinking catalog parts mostly as a vehicle to prove to potential customers your IP can be fabbed to meet their power / performance / yield / cost targets. And if I can buy a couple hundred of these boards for a different project, then I'm even happier.
pama 3y ago
Is there any good benchmark/comparison of the current risk-v boards for use in hobby projects?
- brucehoult 3y ago
  If by "good" you mean "something that's probably about as good as Dhrystone or Coremark but a lot simpler and harder to game" then I've got a benchmark and quite a few results collected on various things over the last seven years here: https://hoult.org/primes.txt https://hoult.org/primes.txt
  - pama 3y ago
    Thanks. So some of these cpu, say VisionFive 2 U74, start to look interesting.
    - pama 3y ago
      Just noting for my own reference that the TH1520 is well within the interesting range.
  - OhMeadhbh 3y ago
    Though... RISC-V support in gnu c and clang have evolved significantly over the last 5 years. Did you re-run any of the tests with more recent compilers? When we were doing benchmarking 5 years ago, it seemed we got slightly better performance every month as Palmer integrated improvements into the gnu toolchain. There were at least a couple months there where we REALLY didn't want to publish benchmarks because we were expecting the numbers to be noticeably better in n days.
    - brucehoult 3y ago
      This is very straightforward code (which I wrote in 2016 before I'd even heard of RISC-V) that maps very cleanly and obviously to instructions and any gcc from the last 20 years will make essentially the same code. A large part of my goal when I wrote it was to make it far more impervious to compiler "improvements" and gaming that Dhrystone and Coremark -- and I think I succeeded very well. The RISC-V B extension's `sh2add` and friends make a small difference -- that's basically the 2.7% gap between the VisionFive 2 and the HiFive Unmatched. If I disable Zba on the VF2 then the times are just about identical.
eigenform 3y ago
I'm curious what your objections to Chisel are! (I don't really care for Scala either .. unless you mean that like, this somehow affects the way that IP is delivered to you as a customer? I thought you just get a big blob of verilog in the end, and I'm not sure how that'd affect you?)
- OhMeadhbh 3y ago
  I'm not the worlds biggest fan of Verilog, but Verilog's semantics are relatively fixed. The interpretation of verilog has remained fairly stable for a decade at least. Chisel is in some ways still a work in progress. So if you want to use it, you have to keep track not only of Chisel productions specific to your design, but also the version of the boom or rocket generator you're using with it. Chisel was never at the center of our design flow, and none of the people I currently work with went to UCB. When we used the Rocket generator we were often "nervous" about whether the version we were using would interpret Chisel productions in the way in which it had previously. But yes... this led us to a working style where we tried very hard to avoid having to use rocket or boom generators. I didn't want to be in the business of maintaining RISC-V Verilog tools. At around the same time we realized RISC-V was overkill and built a very poorly designed Lisp DSL which output Verilog for a dog-simple 6-bit controller. Not an ideal solution to be sure, but it worked better for us than spending a couple years learning Rocket/Scala/Chisel. Nick Tredennick (who I believe was the main designer of the 68k) has a quote in his book "Logic Design: The Flowchart Method": The problem with many texts is that we lie about details. We are sloppy in areas that are not our primary concern. Academics are method fanatics. Practitioners are solution fanatics. In school, we glorify the methods and lie about the sophisticated problems we solved. In industry, we glorify the problems and lie about the sophisticated methods we used. Each side loses credibility the minute one side reads the other's literature. The academic knows that the practitioner's "method" is (ugh!) arbitrary, just as the practitioner knows the academic's "solution is (ugh!) not applicable. Because we oversell method and solution, it takes too long to figure out what really works. I don't want to say Rocket / Chisel / Firrtl is bad, but it always seemed to be more in support of a "process focused" methodology than the "solution oriented" focus I'm used to. If it works for you, I'm absolutely not going to tell you it's a bad idea to use it. It's just too much overhead for the small projects I work on. That being said... SiFive was working on CoC (theorum prover) extensions to validate designs using formal methods. THAT sounds fascinating, but I'm not sure how they would monetize it. [Edit: To recap, I don't have a problem with Rocket / Chisel / Firrtl per se, but they operate at a level I'm uncomfortable with and seem to be less stable than I would prefer. I completely understand this is not the case for many other people.]
cinquemb 3y ago
Makes me think that asia is gonna have this cheap compute available alot faster at the consumer level than anywhere else for at least the next 5-10 years.

camel-cdr 3y ago

> An insane programmer can set LMUL to a value higher than 1, making vector instructions address contiguous blocks of registers. I hope that most code won't use LMUL=1, but LMUL>=1 when possible, otherwise we'd leave performance on the table. The only case I can currently fore see where using LMUL=1 and manually unrolling instead will likely be always beneficial is vrgather operations that don't need to cross between registers in a register group (e.g. byte swapping). > As with all new architectural features, we’ll have to wait and see how useful RISC-V’s LMUL will be. RVV without LMUL would be a lot worse, the entire extension is build around the LMUL concept and it's really nice to work with imo.

dsharlet 3y ago
> The only case I can currently fore see where using LMUL=1 and manually unrolling instead will likely be always beneficial is vrgather operations that don't need to cross between registers in a register group (e.g. byte swapping). What about algorithms where register pressure is an issue? I think the problem with LMUL is it assumes that you always want to unroll the innermost dimension (where the vector loads are stride 1). That's usually, the last dimension I try to unroll, if there are any registers left over. If there is any sharing of data across any other dimension in the algorithm, it's better to tile/unroll those first. Of course, for a simple algorithm, there will be registers left over. But I think more interesting algorithms will struggle on RVV if you must use LMUL > 1 for performance.
- camel-cdr 3y ago
  > What about algorithms where register pressure is an issue Then you'll probably saturate the processor without using a larger LMUL, but I think many algorithms can work with LMUL=2, without running out of registers.
- brucehoult 3y ago
  LMUL (and especially fractional LMUL) isn't for performance, it's for kernels with mixed-element sizes, to maximise the number of variables (and elements) you can keep in registers without spilling. Being able to use LMUL as a way to get the effect of unrolling and hide the pointer bumps and loop control on simple loops on narrow processors, without expanding the code, is just a bonus.

yuumei 3y ago

Just a warning to anyone thinking of using the sifive boards https://forums.sifive.com/t/unmatched-boot-issues/6236 https://forums.sifive.com/t/unmatched-boot-issues/6236

deleted 3y ago
[deleted]
greggsy 3y ago
This just suggests that one board has an undiagnosed issue? Is there some other insight I’m missing?

brucethemoose2 3y ago

Tenstorrent has an 8-wide RISC-V core available for licensing: https://tenstorrent.com/risc-v/ https://tenstorrent.com/risc-v/ ...But I am starting to get suspicious of Tenstorrent. Maybe they have some customers using their designs privately, but I never see any of their hardware used in public.

brucehoult 3y ago
Both Keller joining and announcing they were going to use RISC-V happened in 2021. Why on earth would you expect to already be falling over hardware in 2023? CPU core design takes a couple of years, getting to the first test chips a couple more, and then to mass production a couple more after that.
- brucethemoose2 3y ago
  Indeed, but another company should've announced they are licensing and taping out products on the cores by now, right? If someone starts taping it out right now, the core will be long in the tooth by the time it comes out. I am also suspicious because their 12nm, 2021 Grayskull PCIe cards never materialized: > We’ll be selling Tenstorrent AI PCIe cards, workstations, and servers soon. Stay tuned for availability. https://tenstorrent.com/grayskull/ https://tenstorrent.com/grayskull/
  - snvzz 3y ago
    Soon. Stay tuned. (no concrete promise, thus not late)

ireallywantthat 3y ago

Sorry for my ignorance, but any idea when we can see Desktop Processors powered by RISC-V architecture? It would be breath of fresh air to see new architectures power the desktops.

AlotOfReading 3y ago
You can buy a RISCV SBC and run a Linux desktop on it today. It's just not competitive with x86 in performance or software support. The closest you'll get to that outside arm or x86 is Talos II stuff, which runs PowerNV.
marcodiego 3y ago
I remember this one: https://abopen.com/news/building-a-risc-v-pc/ https://abopen.com/news/building-a-risc-v-pc/ . Since it is from 2019, it is likely there have been some advancements. I also hope for a riscv desktop; it could even be ryf certifiable.
crote 3y ago
The HiFive Pro P550 should be available this summer, for a pretty desktop-like experience. Don't expect RISV-V to directly compete with Intel/AMD on the high end for at least another decade, though.
- snvzz 3y ago
  >Don't expect RISV-V to directly compete with Intel/AMD on the high end for at least another decade Actually 2024. SiFive P870, Tenstorrent Ascalon, SOPHON SG2044, Ventana Veyron, and more.
  - rwmj 3y ago
    Rivos too ...
    - snvzz 3y ago
      Rivos hasn't announced anything. There's several other companies we know are working on processors but haven't announced a thing.

phkahler 3y ago

We still need a an open and free GPU to pair with this in a SoC.

deleted 3y ago
[deleted]
marcodiego 3y ago
Hantro and panfrost fill this gap. No blob is required afaik.
- MobiusHorizons 3y ago
  While very cool, open source drivers for propriety a proprietary gpu design is not quite the same as open silicon or open gpu isa, which is what I think the parent was asking for.
0xDEF 3y ago
This is not an open and free CPU. It just implements the open and free RISC-V instruction set. Judging by the SiFive business model they will in the future inevitably add proprietary extensions.

sylware 3y ago

We will need some sort of soft tablesheet in order to know how to write assembly to leverage instruction fusion in a best effort fashion. I wonder how many GHz this µArch would reach with TSMC 3nm.

sylware 3y ago
Come on, with ASML EUV-HighNA with the smallest feature set we can have.

synergy20 3y ago

SiFive is now a IP license shop I think? similar to Andes from Taiwan who also sells RISC-V cores. Difference is that SiFive is more on the desktop CPU while Andes is more on the embedded space. In the Machine Learning startup field, RISC-V is the most popular choice these days. RISC-V also becomes a national priority for China as far as I can tell, it won't surprise me the best RISC-V designs will be from there.

codedokode 3y ago

> A 32 entry iTLB helps cache virtual to physical address translations on the instruction side. Why are TLBs so small? Are they super expensive or what? With 32 entries TLB it can cover only 1 Mb of RAM if using legacy 4k pages.

johndoe0815 3y ago
Yes, TLBs are pretty expensive (in area and power) since they are associative memories. The virtual (non-offset) part of an address to be translated is compared to all TLB entries simultaneously to keep latencies down since the TLB is on the critical path from CPU to memory. Accordingly, you need one comparator (lots of XOR gates in a simple implementation) per TLB entry.