6 ms·

On the PS3 SPU cores, the best "does everything" instruction was the single "rotate and mask" series of instructions which was the underlying implementation of

On the PS3 SPU cores, the best "does everything" instruction was the single "rotate and mask" series of instructions which was the underlying implementation of all rotates, shifts, and bitfield extraction instructions. That architecture is still my favourite years on - every register was vectorised by default, and the instruction was the minimalistic set to achieve a lot of unusual operations that were incredibly useful for graphics or signal processing work. Often you couldn't find an exact instruction to do what you wanted, but if you studied the documentation long enough, you'd find one that generalised it and actually did do what you wanted, as well as gracefully handling loads of other edge cases you hadn't thought of - for instance the various instructions to create shuffle masks so that lots of byte/word/long re-ordering operations could be done with the single shuffle instruction, which could be used to emulate unaligned memory access using aligned-only memory accesses. Not exactly weird, but on the PowerPC side "eieio", is my most favourite name for an instruction on any architecture - without fail, every time I come across it, I start humming Old McDonald!

Vogtinator 3y ago
There are similar instructions on PowerPC (rlwinm) and bfi/ubfx instructions on ARMv8.
Everdred2dx 3y ago
Not a whole lot of asm experience here- what does it mean for a register to be vectorized?
- nwallin 3y ago
  SIMD. Instead of having one value in one register, you have several values per register. (usually a small power of 2. SSE is 4 floats per register. AVX512 is 16 floats per register.)
  - corysama 3y ago
    And, when you perform an operation on a register, like an add, the operation works on all of the values in that register simultaneously in a single instruction.
adamnemecek 3y ago
Do you happen to have a link to said docs?
- jjtheblunt 3y ago
  I'd start here https://www.psdevwiki.com/ps3/Cell_Programming_IBM https://www.psdevwiki.com/ps3/Cell_Programming_IBM
- ralferoo 3y ago
  It looks like my memory is playing tricks and the combined instruction that does everything was just on the PPU (the PowerPC part) and not the SPU. But the SPU ISA docs are available in many places, just googled and found this mirror: http://www.ece.stonybrook.edu/~midor/ESE545/SPU_ISA_v12.pdf http://www.ece.stonybrook.edu/~midor/ESE545/SPU_ISA_v12.pdf - the various shifts start on page 117, but they're simpler than I remember - shift left in various forms, rotate (right) and mask (i.e. shift right) and rotate (right). But, even looking at the instructions, it's not immediately obvious that every instruction is operating on a 128-bit vector - e.g. shl operates on 4 32-bit fields at once,and shlh operates on 8 16-bit fields at once, and so e.g. a single instruction can even shift by different amounts. Almost all instructions operate this way, only a few only use the first field in a vector, e.g. conditional branches (brz, brnz, brhz, brhnz). The other rotate instructions are interesting - you can do bitwise rotate across the entire 128-bit vector, rotate by bytes (very useful for memory accesses) and the wonder instruction shufb (shuffle bytes, see page 116) which allows each byte of the result to be pulled from a specific byte in of 2 vectors, or a constant (0,0x80,0xFF) which allows you do do all manner of things for example byte order swapping or different values together. So, you have this really powerful instruction set that's vectorised on almost every instruction, and then you have a massive 128 registers per core coupled with 32KB local cache memory which is single cycle access. It's an absolute joy to program for on anything which will fit into the 32KB local cache (which includes your program). The only downside is that anything that doesn't fit into 32KB requires you to start a DMA request to copy a chunk to or from main memory, and wait for it to complete and/or continue doing other work in the background. With suitable workloads operating on 10KB or less, many people used this in a true double-buffered fashion, so the next set of data was transferring while you were processing the previous set, but this made lots of tasks quite complicated and many developers found it too hard to make good use of the SPU, and so it was often sadly under-utilised. One interesting effect though, is that DMA'ing your buffers took a similar time to a cache miss on the PowerPC cores, so actually even a naive approach that always triggered a small DMA from main memory in parallel with other operations often wouldn't see much latency and might still even be quicker than running the same task on the PowerPC cores where there was less opportunity for doing other work during a cache miss. Another interesting feature of this CPU is that you can do a pre-emptive branch prediction so that the instruction cache is already full when a branch is takenm meaning that a branch can execute in a single cycle. Coupled with indirect branch (i.e. using a register value), you can give a CPU a branch hint in advance of the end of a loop as to whether it'll terminate or not and also avoid stalls. In some cases this could outperform the x86 branch prediction that was common at the time, which was just maintaining a cache of the last target of recent branches. Overall, SPU programming was tough to master, but once you got something working the performance was phenomenal. I think that's why I liked it so much - because the sense of accomplishment was so tangible once you'd battled through it and emerged the other side with some amazing code. But nowadays, the power it provided, that was unheard of at the time (7 cores at 3GHz), isn't anything special over a mid-range i9.
icelusxl 3y ago
> "rotate and mask" series of instructions Sounds a lot like the PowerPC's rlwinm instruction. The PowerPC 600 series, part 5: Rotates and shifts https://devblogs.microsoft.com/oldnewthing/20180810-00/?p=99465 https://devblogs.microsoft.com/oldnewthing/20180810-00/?p=99...
- throwawaylinux 3y ago
  SPU is significantly derivative from PowerPC, so that's quite expected.
Findecanor 3y ago
Continuing the tradition of having ridiculously -named instruction, when PowerPC went 64-bit, it got a rotate-and-mask instructions named `rldicl` - Rotate Left Doubleword Immediate then Clear Left
- deleted 3y ago
  [deleted]
ktm5j 3y ago
There's also a gnu error code called EIEIO: https://www.gnu.org/software/libc/manual/html_node/Error-Codes.html https://www.gnu.org/software/libc/manual/html_node/Error-Cod...
- moritzwarhier 3y ago
  And apparently also > EGREGIOUS and > EGRATITUOUS and... lots of stuff ^^
- cosmojg 3y ago
  Macro: int ED “?.” The experienced user will know what is wrong. Macro: int EGREGIOUS “You really blew it this time.” You did what? Macro: int EIEIO “Computer bought the farm.” Go home and have a glass of warm, dairy-fresh milk. Macro: int EGRATUITOUS “Gratuitous error.” This error code has no purpose.

Vogtinator 3y ago

There are similar instructions on PowerPC (rlwinm) and bfi/ubfx instructions on ARMv8.

Everdred2dx 3y ago

Not a whole lot of asm experience here- what does it mean for a register to be vectorized?

nwallin 3y ago
SIMD. Instead of having one value in one register, you have several values per register. (usually a small power of 2. SSE is 4 floats per register. AVX512 is 16 floats per register.)
- corysama 3y ago
  And, when you perform an operation on a register, like an add, the operation works on all of the values in that register simultaneously in a single instruction.

adamnemecek 3y ago

Do you happen to have a link to said docs?

jjtheblunt 3y ago
I'd start here https://www.psdevwiki.com/ps3/Cell_Programming_IBM https://www.psdevwiki.com/ps3/Cell_Programming_IBM
ralferoo 3y ago
It looks like my memory is playing tricks and the combined instruction that does everything was just on the PPU (the PowerPC part) and not the SPU. But the SPU ISA docs are available in many places, just googled and found this mirror: http://www.ece.stonybrook.edu/~midor/ESE545/SPU_ISA_v12.pdf http://www.ece.stonybrook.edu/~midor/ESE545/SPU_ISA_v12.pdf - the various shifts start on page 117, but they're simpler than I remember - shift left in various forms, rotate (right) and mask (i.e. shift right) and rotate (right). But, even looking at the instructions, it's not immediately obvious that every instruction is operating on a 128-bit vector - e.g. shl operates on 4 32-bit fields at once,and shlh operates on 8 16-bit fields at once, and so e.g. a single instruction can even shift by different amounts. Almost all instructions operate this way, only a few only use the first field in a vector, e.g. conditional branches (brz, brnz, brhz, brhnz). The other rotate instructions are interesting - you can do bitwise rotate across the entire 128-bit vector, rotate by bytes (very useful for memory accesses) and the wonder instruction shufb (shuffle bytes, see page 116) which allows each byte of the result to be pulled from a specific byte in of 2 vectors, or a constant (0,0x80,0xFF) which allows you do do all manner of things for example byte order swapping or different values together. So, you have this really powerful instruction set that's vectorised on almost every instruction, and then you have a massive 128 registers per core coupled with 32KB local cache memory which is single cycle access. It's an absolute joy to program for on anything which will fit into the 32KB local cache (which includes your program). The only downside is that anything that doesn't fit into 32KB requires you to start a DMA request to copy a chunk to or from main memory, and wait for it to complete and/or continue doing other work in the background. With suitable workloads operating on 10KB or less, many people used this in a true double-buffered fashion, so the next set of data was transferring while you were processing the previous set, but this made lots of tasks quite complicated and many developers found it too hard to make good use of the SPU, and so it was often sadly under-utilised. One interesting effect though, is that DMA'ing your buffers took a similar time to a cache miss on the PowerPC cores, so actually even a naive approach that always triggered a small DMA from main memory in parallel with other operations often wouldn't see much latency and might still even be quicker than running the same task on the PowerPC cores where there was less opportunity for doing other work during a cache miss. Another interesting feature of this CPU is that you can do a pre-emptive branch prediction so that the instruction cache is already full when a branch is takenm meaning that a branch can execute in a single cycle. Coupled with indirect branch (i.e. using a register value), you can give a CPU a branch hint in advance of the end of a loop as to whether it'll terminate or not and also avoid stalls. In some cases this could outperform the x86 branch prediction that was common at the time, which was just maintaining a cache of the last target of recent branches. Overall, SPU programming was tough to master, but once you got something working the performance was phenomenal. I think that's why I liked it so much - because the sense of accomplishment was so tangible once you'd battled through it and emerged the other side with some amazing code. But nowadays, the power it provided, that was unheard of at the time (7 cores at 3GHz), isn't anything special over a mid-range i9.

icelusxl 3y ago

> "rotate and mask" series of instructions Sounds a lot like the PowerPC's rlwinm instruction. The PowerPC 600 series, part 5: Rotates and shifts https://devblogs.microsoft.com/oldnewthing/20180810-00/?p=99465 https://devblogs.microsoft.com/oldnewthing/20180810-00/?p=99...

throwawaylinux 3y ago
SPU is significantly derivative from PowerPC, so that's quite expected.

Findecanor 3y ago

Continuing the tradition of having ridiculously -named instruction, when PowerPC went 64-bit, it got a rotate-and-mask instructions named `rldicl` - Rotate Left Doubleword Immediate then Clear Left

deleted 3y ago
[deleted]

ktm5j 3y ago

There's also a gnu error code called EIEIO: https://www.gnu.org/software/libc/manual/html_node/Error-Codes.html https://www.gnu.org/software/libc/manual/html_node/Error-Cod...

moritzwarhier 3y ago
And apparently also > EGREGIOUS and > EGRATITUOUS and... lots of stuff ^^
cosmojg 3y ago
Macro: int ED “?.” The experienced user will know what is wrong. Macro: int EGREGIOUS “You really blew it this time.” You did what? Macro: int EIEIO “Computer bought the farm.” Go home and have a glass of warm, dairy-fresh milk. Macro: int EGRATUITOUS “Gratuitous error.” This error code has no purpose.