9 ms·
The Death of SRAM?
- Gualdrapo 4y agoOh. That SRAM. For a moment I imagined Bauke Mollema was cheering up reading this[0]. [0] https://www.youtube.com/watch?v=Tsk3zAZyLaQ https://www.youtube.com/watch?v=Tsk3zAZyLaQ
- davidw 4y agoYeah... started thinking "uh oh, where am I going to get replacement bits for my MTB?!"
- turminal 4y agoAge restricted and wants me to sign in :(
- LeifCarrotson 4y agoThey're talking about the bicycle component vendor named SRAM: https://www.sram.com/en/sram/mountain https://www.sram.com/en/sram/mountain
- to11mtm 4y agoIt's been forever since I've been deep into biking so I'm afraid to click the link. 9 speed was already almost too much for a 'casual-enthusiast' [0]. But in general, Shimano or Campy is my preference for drivetrain [1] and Avid/Shimano for brakes [2]. [0] - I've blown out 9 speed cassette in less than 1k miles due to my riding style (skipping gears). NEVER had a similar problem on the 8 speed cassettes or 5 speed freewheels I would roll on. [1] - Ok so I had a SRAM grip-shift break in a way it shot plastic in my face which was a terrible first impression. But also I've had 'issues' with a lot more SRAM vs Shimano when building/maintaining bikes. And then there was the Truvativ 3 speed road crank that could never get adjusted right (FWIW, I got the same 'model' as a double for a tandem and it was bliss... but that is my point about QC.) Also, that mess that was 'power spline'. Tore that up before in less than 500 miles. [2] - In the day I was all about Speed-Dial 7s[3] for levers and BB7s for brakes (Very adjustable, none of the pains of fluid based disc brakes) and Shimano had a bad habit of trying to make things proprietary (center-lock disc hubs). [3] - SD7s are the best retrofit-bike thing on the planet, because they can make all sorts of old/new brake combinations work with a consistent set of levers!
- LeifCarrotson 4y agoIf it's been forever, SRAM might be worth reconsidering. Shimano and Campagnolo are both hundred-year-old companies, SRAM is much newer. SRAM is twice as big now as it was 10 years ago, they've improved by leaps and bounds compared to what you likely remember.
- zwieback 4y agoSimnplex forever!
- CyberDildonics 4y agoYou thought a link to wikichip was about cycling?
- nordsieck 4y ago> So where do we go from here? The reality is that currently, the only viable alternative to SRAM is simply more SRAM, and therefore we expect to see SRAM directly consuming more area. Betteridge's law strikes again.
- richardjam73 4y agoIt's more of an extinction than a death. If SRAM can't shrink it will eventually be replaced by other technologies that can.
- EarlKing 4y agoNot exactly. SRAM will be replaced by other technologies that can if and only if there is a commensurate increase in speed (since that's the whole point of using SRAM over DRAM).
- _hypx 4y agoThere's already talk of STT-MRAM or SOT-MRAM replacing SRAM. They offer similar performance while also being non-volatile. If SRAM scaling ends, this becomes a much more promising technology. https://semiengineering.com/sot-mram-to-challenge-sram/ https://semiengineering.com/sot-mram-to-challenge-sram/
- marcosdumay 4y agoGood luck making the next step of memory miniaturization with a magnetic technology. There's a reason magnetics were popular when circuits where finger-sized, and completely disappeared when they got smaller. It may not be impossible to make 3D magnetic circuits that match 2D electronic ones, but it's very close to that.
- _hypx 4y agoThese things are more accurate called "spintronics." They are very different from conventional magnetic recording technologies.
- ajross 4y agoWasn't this already sorta common knowledge? Almost the tricks in recent process generations to increase density have been vertical. FinFETs et. al. work by stretching the transitor upwards to increase gate area, so it drives harder and you need fewer of them to implement the same logic. But the actual pitches of the gate and fins haven't been changing nearly as fast, so the smallest circuits aren't seeing much benefit. A SRAM cell is 6-8 transistors all connected internally with only a read and data line coming out (well, and the power rails). That's already horizontally packed, making the transistors beefier won't help anything.
- userbinator 4y agosuch as higher density at lower read/write specifications, non-volatility capabilities, lower read-write cycle capabilities Also known as NAND flash, i.e. the chips that actually wear out. Another example of planned obsolescence creeping in to what used to be effectively unlimited lifespan for "solid state" electronics?
- to11mtm 4y agoThere's different options for different things. You have: - EEPROM for low/medium frequency of update, small size, persistence - NAND flash for low/medium frequency of update, semi-arbitrary size, persistence - eDRAM variants (Mosys '1T SRAM' comes to mind, which is still DRAM but has more dedicated Row/Column circuitry vs SDRAM's RAS-CAS timing shenanigans) for frequent update, volatile or maybe battery backed storage, non-persistent Which... we -kinda- see in some layers already, as eDRAM has gone from 'fancy server procs and halo mobile chips' to a -little- more mainstream.
- codebje 4y agoNot really, no. For a start, I don't think NAND flash itself is an example of planned obsolescence: its main predecessor is spinning rust platters, which were notorious for sudden catastrophic failures. Spinning rust replaced, more or less, magnetic tape, which does have an effectively unlimited lifespan (it's more likely that you won't find a working tape reader than that you'll find properly stored tape is no longer readable) but is otherwise a terrible storage medium. But more on point, this article's context is static ram on-die for a microcontroller or similar. One possible replacement for SRAM is magneto-resistive RAM (MRAM) - it's not quite as fast as SRAM but close enough for many applications, it's higher density than SRAM, so it'll take up less die space, and it's non-volatile so µCs can ditch the NOR flash often used for code storage. One great thing about MRAM is that it has no write wearing: it has an effectively unlimited lifespan, without all the downsides of magnetic tape. I look forward to seeing it (or similar technologies) in microcontrollers in the future.
- zozbot234 4y agoMagnetic tape doesn't have unlimited lifespan. You can store it almost indefinitely, but reading and writing tape will cause quite a bit of wear and tear on the media. But yes, it would be great if MRAM turned out to have such a favorable profile.
- mjevans 4y agoNot the death, but AMD's chiplets at different process nodes is the approach of the future. One of the slides I remember from an AMD presentation in recent Gamers Nexus videos showed curves for cache, logic, and a third curve across process nodes. SRAM has desirable properties; simplicity, self sustaining state, latency. The flattening curves follow the approach to the physical limits of doped silicon. It'll be interesting to see if another electron based but different semiconductor or another method of computing entirely (maybe photonics or some other range of the EM spectrum?) continues the rise in density or if we instead focus more on optimizing hardware and software.
- arcticbull 4y agoYeah, basically. The 3D-VCache approach reduces the need for scaling by increasing the surface area available. It's not quite as important to get the absolute smallest transistors if you can use a larger process node, make the cache the same size as the entire rest of the die, then stick it on top. You're no longer competing for space on the same die as the functional units.
- selectodude 4y agoCooling those stacked chips is a nightmare though. They’ll have to figure that out.
- zozbot234 4y agoAIUI AMD's commercial V-Cache chips are slightly lower max clock speed than comparable chips without V-Cache, and thermals are probably why. It's still a huge win for most applications, nonetheless.
- selectodude 4y agoOh absolutely. I have one and the 96MB of cache is worth the 500MHz I lose.
- williamDafoe 4y ago"We now pause all CPU activity as we refresh the DRAM for all the registers.. " - sheesh! That's not going to happen because the process tech for dram is tuned for capacitance and the process tech for SRAM and CPUs is tuned for speed... How about, "this CPU is using 3D nandram and is rated only for one quadrillion instructions or one year whichever one comes first!" Imagine a compiler that has to do wear-leveling on the registers!
- berkut 4y agoIs it me reading it wrong, or does the second paragraph of the "Impact" section not match the numbers from the diagram below it? It seems they're offset for the generations?
- r00fus 4y agoCrickey I got worried that Shimano somehow got a monopoly.
- comprev 4y agoLong life Microshift! https://www.microshift.com/ https://www.microshift.com/
- trynumber9 4y agoGiven this poor scaling maybe we will see some CPUs like AMD's Milan-X but taken to the next level: - Remove all or almost all L3 from the CPU die built with the best available logic process, like N3E - Stack a last level cache die with relatively cheaper process that has similar or better SRAM density, like N5
- AnthonyMouse 4y agoAdding more levels of cache is a time-honored tradition, and it works. For example, with the M1, Apple tied the DRAM interface to the CPU. That got them more bandwidth, but then you can't upgrade the memory, which is weak. But why not do both? Have e.g. 8GB of high-bandwidth DRAM soldered to the board, essentially that amount of L4 cache, but keep the DIMM slots where you can add arbitrarily more memory with less bandwidth.
- Palomides 4y agolater Xeon Phi chips had this, 16GB of on-package RAM with 4x the bandwidth of the external RAM
- fulafel 4y agoIBM has been doing this for a long time. Eg here's one mainframe CPU with 960 MB of L4: https://fuse.wikichip.org/news/3383/ibm-doubles-its-14nm-edram-density-adds-hundreds-of-megabytes-of-cache/ https://fuse.wikichip.org/news/3383/ibm-doubles-its-14nm-edr... (They also have DRAM in other levels of cache hierarchy except L1, with L2 running at 5+ GHz)
- legulere 4y agoThere’s potentially even more layers. Compute express link allows to expand the system with even more RAM slowly through PCIe And already now you have NUMA where performance is different and depending on which core you are.
- Vogtinator 4y agoIBM are the masters of this: https://www.anandtech.com/show/16924/did-ibm-just-preview-the-future-of-caches https://www.anandtech.com/show/16924/did-ibm-just-preview-th... Processors can use the L2 cache from other (remote) processors before reaching out to DRAM.
- BirAdam 4y agoI don't know if this is a "we can't scale SRAM" as much as it is that there's very little benefit from scaling SRAM. DRAM, for example, cannot be shrunk because the capacitors that enable DRAM physically cannot shrink and still function properly. SRAM is just six transistors wired to store a bit. There is nothing stopping the use of chiplets manufactured with different process nodes... AMD already does this.
- throwawaylinux 4y agoThere is a lot of benefit for scaling SRAM, because it makes up a large fraction of chip area on a lot of designs that use leading edge nodes (e.g., CPUs), and chip area ~= manufacturing cost for high volume products. SRAM cells are constrained by certain features that are not able to shrink much https://semiwiki.com/forum/index.php?threads/sram-cell-scaling.12722/ https://semiwiki.com/forum/index.php?threads/sram-cell-scali... the logical schematic of an SRAM does not show anything about how a real cell is physically constructed. Foundries and high end design companies have teams doing SRAM design.
- zozbot234 4y ago> Foundries and high end design companies have teams doing SRAM design. Yep, this is also why the claim in this article title might just be a bit overstated. There's a mention that TSMC will likely announce optimized SRAM cell designs for N3-like nodes at some point, and these designs can be expected to involve some scaling.
- nsteel 4y agoThe mention is that Wikichip expect optimized SRAM cells but there's nothing to support this. I'm not so sure given the problem they've had so far.
- pclmulqdq 4y agoIt's more likely that we will 3D stack our SRAM on top of (or underneath, depending on heat management) our logic chips, and there may be special SRAM-optimized processes if this occurs. 6T SRAM has a lot of issues in leading-edge process nodes that are optimized for logic, since it depends a lot on the analog characteristics of the transistors used. Separating SRAM and logic processes will eventually make sense if we find that SRAM and logic can't scale on the same process. L1 and L2 caches on the logic die can be 8T SRAM (which is, I think, already in the L1 cache of Intel CPUs) if needed.
- f_devd 4y agoAMD had already done that with their 3D V-Cache, and to your point of SRAM & Logic not scaling on the same process they have also been working on that with the just released RDNA3 GPUs (The I/O-die is 7nm and the Logic die is 5nm IIRC).
- TanjB 4y agoThose cell sizes are theoretical anyway. They do exist, but on sample chips optimized for SRAM. If you design a chip and select an IP macro for SRAM the density you actually get may be 3x or larger per bit. This is due to compromises on the process the rest of the chip goes through, the need for row and column periphery, ECC, and ports. One advantage the Z-cache has at AMD is the cache chip appears to be optimized for SRAM. It has 2x the capacity of the cache on the CPU chip even though it directly matches the overall cache outline on the base. The main problem with scaling is that SRAM found an optimal layout in FinFET with no significant wiring issues. While scaling from 7nm on down none of the tricks that benefit logic density - fewer lines, reduced gaps, contacts over active gate - SRAM does not need them. It was already optimal. The only thing it benefits from is honestly finer features, which is happening only slowly. The next major jump expected is CFET where going vertical is matched by a new optimal pattern that takes advantage if the N and P being above each other. That is generally expected for N2/20A processes.
- ChuckMcM 4y agoSigh. That some circuits are not getting smaller is not really all that newsworthy. Circuit folks have looked at scaling issues for decades, this wasn't surprising. That said, there are exciting things in stacking layers, and inter chip layer connects (chip on chip technology) that could make more feature dense (if slightly taller) chips. Heat dissipation continues to be an issue as well. As someone who started at Intel in the 80's though, the amount of "surplus" cheap resources resembles your typical laptop with gigabytes of RAM and terabytes of disk, there is a huge amount of gain to be had in re-architecting software as there is gain to be had in re-architecting the micro-architecture of SoCs.
- ChrisLTD 4y agoIt's hard to avoid the conclusion that software today isn't 1,000s of times better than software in the 1990s, but it certainly uses 1,000s of times the resources.
- vlovich123 4y agoI wonder if we’ll have smarter cache eviction strategies. For example, when there’s a context switch we pollute the cache and it takes time for it to ramp up. I wonder what it would look like if the cache for each context was fully flushed out (modulo addresses marked as shared across processes), particularly on a kernel switch (not to RAM for perf reason but maybe to a much larger L4 cache or at a minimum the L1/L2 caches could be context swapped). That would make the existing cache far more efficient. Similarly, what if some data could be marked as “infrequently used” and using a different cache slab. An example of that might be when the OS is compressing unused pages - it’s better to use a separate cache space for things like that to avoid evicting the useful stuff. Similarly, what would it look like if we dedicated CPU cores to running the kernel and other cores executed the kernel through io_uring and futexes only. That could significantly reduce cache pollution although there may be more cross cpu cache shoot down? Just for context, most L3 caches today are the size of the entire RAM from 20 years ago. You’d think that you should be able to run the hyper visor totally out of L3 cache. Also some of these alternate architecture would also be inherently more secure because it would be harder to exploit side channel attacks across contexts.
- mazurnification 4y agoUp to this point being firmly in the camp that Moore's law is not dead - this is first data point that convincing enough for me to reconsider my stance. The problem is not that SRAM is important or not. SRAM cell is basically one of the simplest circuit actually doing something useful, where most things important for actual design are in play (not only transistors size, but also its parameters, parastics, manufacturability etc). Also since it is so simple and important circuit it is hard to argue it was not optimized to the moon and beyond. If this do not scale - girl we are in trouble. ) Although signs of slow down were plenty beforehand if you squint your eyes it was possible to attribute it to Intel dropping ball and rest of industry catching up its 1.5 generation lead. (Industry converging back to long term trend).