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Intel enters a new era of chiplets
- pyrolistical 4y agoOnly took 5 years https://www.pcgamer.com/intel-slide-criticizes-amd-for-using-glued-together-dies-in-epyc-processors/ https://www.pcgamer.com/intel-slide-criticizes-amd-for-using...
- washadjeffmad 4y agoHas Intel ever released a benchmark or marketing comparison that wasn't the filtering equivalent of spelling and grammar mistakes in spam emails? If you notice it for what it is, you're not their target demographic. Their whole sour grapes culture is just bizarre to me.
- paulmd 4y agoEh, they were criticized for "glued-together" processors in the Pentium D/Core2 era, so a little turnabout is fair play. https://www.anandtech.com/show/1656/2 https://www.anandtech.com/show/1656/2 https://pcper.com/2006/11/intel-core-2-extreme-qx6700-processor-brings-quad-core-computing/ https://pcper.com/2006/11/intel-core-2-extreme-qx6700-proces... Also, let's be honest. First-gen Epyc was glued-together nonsense. It was very much NUMA, it performed weird, the cause was the weird chiplet design (no IO die at that time). It was fair to criticize it on that basis. It had far less cache and much higher latency than the designs that followed, and it felt far more NUMA as a result. Hyperscalers agreed and turned their noses up at it after some test installations, and decided to wait for Rome - which was much much better in those areas. But Naples was bad and that shouldn’t be sugarcoated. I don’t really get why people are always so miffed by Intel saying that, it was a criticism that had been leveled against them, and they were right in applying that criticism to AMD, it was a quirky server design glued together out of consumer dies, it suffered all the same downsides as Intel’s own “glued-together” designs. Didn’t they really just… call a spade a spade?
- selimthegrim 4y agoI believe Orange County Choppers even poked a little fun at them.
- jeffreygoesto 4y agoWhat will sit on top of UCIe software wise? Any standards coming up there?
- whalesalad 4y agomicroservies for silicon
- nwah1 4y ago>Intel also has a packaging line that spans 2D technologies as well as 3D technologies like its Foveros line. Very cool
- midislack 4y agoPentium Pro used "chiplets." Ironically Intel mocked AMD recently for it.
- urthor 4y agoWhat's old is new again. Had a chat with an old timer whl was doing horizontally scaling compute with thr IBM A400. 25 years later it's the starry eyed wonder of the 2010s.
- Flankk 4y ago
- danaris 4y agoI've never been clear on how much Intel couldn't make cooler chips, and how much they just can't admit to themselves that it matters (and thus didn't try very hard).
- yakkityyak 4y agoHaving worked there under BK and Bobby it is very clear why. They didn't invest anything into engineering. Even today their comp is peanuts compared to any other company in the tech industry.
- jamiek88 4y agoBbbbbbut benchmarking………market survey……advanced analytics……some HR goober said that we are ‘competitive’.
- stavros 4y agoWhy didn't AMD? Is the M2 that much better than Ryzen, for example?
- carlycue 4y agoApple Silicon will have the title of world's best designed silicon for the foreseeable future. The only way for AMD and Intel to be competitive is if they can match the performance/watt, thin-ness, fan-less and battery life of the M2 MacBook Air. Forget having all of these things at once. AMD and Intel chips can't even function in fan-less enclosures!
- SteveNuts 4y agoApple has the luxury of being able to design the chips and the chassis together to dissipate heat. Intel and AMD chips go to OEMs
- zaroth 4y agoAnd the operating system too, so they can fully leverage all the special features on the chip to improve UX. Once you have critical mass being able to have enough experienced engineers up and down the whole stack, and you’ve figured out an organizational structure that allows them to work together efficiently, I don’t see how you can beat the vertical integration in a world where the fabs Apple can use are actually better than Intel’s own fab.
- zaroth 4y agoCorrect me if I’m wrong, but a decade ago Intel would probably have said their fab/process node was their moat? I know nothing about chip design, but like most things, I feel like one exceptionally brilliant tech lead surrounded by a group of say ~100 merely very smart collaborators can make a world class ARM based processor-design. A mere $100mm annually in hiring and overhead? The rest of Apple’s advantage comes from being able to actually hire the best, and being their own customer at scale, which means being able to buy first place in line at the fab with billions of dollars of cash. This is perhaps less true now that the chip has so many specialized areas on the die? Like, does the neural engine get allocated a certain mm^2 and certain number of bus lanes, and then a fully separate team of 100 designs it? I suspect the neural engine part of the chip is actually super simple to design, it’s the tight coupling with the OS and getting apps to properly leverage it which is tricky.
- citizenpaul 4y agoSomething about this gives me the under the skin creepy feel of piles of "locked" resources sitting on peoples desk going to complete waste. Like when they used to sell mainframes with excess processor capacity then you would pay to unlock the processor that was already there if you need it. If not it was simply manufactured to sit unused in a mainframe its entire life, then be thrown in the trash. I didn't specifically see anything that said this in the article but there is a TON to digest in there though mdular hardware always has that built to waste vibe. Even if they claim the opposite.
- to11mtm 4y agoIIRC they have something like that but different in the works, 'Software Defined Silicon' (SDSi) is what it's called.
- bee_rider 4y agoI'd assume the opposite actually. Chips always have to be binned. But previously a chip would have to be binned down to it's worst component I guess -- if they had a chip with great CPUs but the GPUs were a little wonky, and they didn't have an appropriate processor line for that combo, they'd have to bin the whole thing down to low-tier. Now they can instead match up the good CPUs and the good CPUs. Plus they'll be able to satisfy some of their lust for SKUs by mixing and matching tiles, rather than making a bazillion slightly bins.
- Animats 4y ago> lust for SKUs That's so Intel. All 37 variants of the Intel Core i9 CPU: [1] [1] https://www.intel.com/content/www/us/en/products/details/processors/core/i9/products.html https://www.intel.com/content/www/us/en/products/details/pro...
- toast0 4y agoCore i9 isn't a useful thing to complain about SKUs for. There's probably been thousands of Pentium products at this point. What you want to look at is how many SKUs for an architecture, like say Alder Lake for Desktop[1]. Do we really need 5 to 7 SKUs at 16, 12, 6, or 4 cores, but only 2 SKUs at 10 cores, and 4 SKUs at 2 cores? [1] https://ark.intel.com/content/www/us/en/ark/products/codename/147470/products-formerly-alder-lake.html#@Desktop https://ark.intel.com/content/www/us/en/ark/products/codenam...
- aidenn0 4y agoI remember when some of the old Slot-1 P3 cpus had off-die, but on-board cache (The Katmai did, the Coppermine did not).
- to11mtm 4y agoYeah... Back in the day, as another comment mentioned, the PPro had a 'chiplet' style configuration where The CPU and Cache were on the same chip but separate dies. The problem with this was the CPU and Cache had to be bonded to the chip first, then tested, and if either was bad, game over. Additionally, at the time die size was at more of a premium, in the case of a PPro, 256Kb of cache was close-ish to 2/3 the size of the CPU die. [0] The P2, Katmai P3, and the Athlon 'Classic' (Pluto/Orion) used offboard cache; This was far better from a yield standpoint (I'm assuming the cache chips could either be tested before install, or were easier to rework) but limited their speed. It's crazy to think that the Katmai P3 itself had around 9.5 Million Transistors, but the 512Kb of cache was another 25 Million on it's own! [0] - https://en.wikipedia.org/wiki/Pentium_Pro#/media/File:Pentiumpro_moshen.jpg https://en.wikipedia.org/wiki/Pentium_Pro#/media/File:Pentiu...
- throw0101a 4y ago> I remember when some of the old Slot-1 P3 cpus had off-die, but on-board cache I remember when you had to buy an extra processor to get floating point. * https://en.wikipedia.org/wiki/X87 https://en.wikipedia.org/wiki/X87 At one point there were video game(s) with 'extra' functionality that was only available with this hardware 'upgrade': * https://en.wikipedia.org/wiki/Falcon_3.0 https://en.wikipedia.org/wiki/Falcon_3.0 (Get off my lawn.)
- aidenn0 4y agoYou're probably not that much older than me, the first PC I used was a Z80 based system (it came standard with a floppy drive though)
- pfoof 4y agoIt has kind of FPGA vibes iiuc
- nsteel 4y agoAs of this comment, there are 53 occurrences of "apple" and 4 of "chiplet" in the comments here (three from the same comment). And to comment on topic, this mix of processes, each optimised to the task at hand and all on the same package sounds perfect for Intel. But I wonder how accessible it is for regular TSMC customers. We've had chiplet presentations, I don't recall anything like this being offered, despite requiring extremely high bandwidth for our application.
- to11mtm 4y ago> But I wonder how accessible it is for regular TSMC customers. TSMC is part of the UCIe (Universal Chiplet Interconnect) consortium, so I'd assume they have some capability. But the other members are ARM, Intel, AMD, Qualcomm, and Samsung... so I'm not sure if it's a matter of you have to be 'working in that club' or if TSMC can provide help on custom solutions.
- yaantc 4y agoAMD fabs at TSMC (and GloFo for the I/O die before, but this has moved to TSMC too recently) and has been using chiplets. TSMC does have 2.5 and 3D packaging for this. But it's still up to the fabless client of TSMC to design the chip. In other words, TSMC provides the enabling tools, but it's up to their client to use them. For now it's for the big players.
- nsteel 4y agoIndeed. And they've got designs using at least two different processes (one for compute, another for IO) but the article has examples using 4 or 5! I just can't see anyone else going as far as that.
- yaantc 4y agoWell, AMD has a few "3D V-cache" variants with an extra cache/memory die, so it's 3 chiplets types today. And these chips do not have an integrated GPU, which it would make sense to have on a separate die (what Intel announced). I wouldn't be surprised that after a period of evolution and leap frogging it ends up in pretty similar spots. They have similar constraints and tools after all.
- Animats 4y agoThe article notes some advantages of being able to use different processes for different wafers, but there's not much more on that. It might be helpful if you wanted different fabs for memory and compute, or for flash type memory. Anyone know what they're getting at here? There are situations when you really need that, but they mostly involve imagers. The Advanced Scientific Concepts flash LIDAR had a two-chip stack, with the light detectors made with InGaAs technology. The counters and timers were ordinary CMOS. This also shows up in some IR sensors.
- yaantc 4y agoMemories have their specialized processes indeed, but there are other reasons to specialize. New nodes are fine for logic, but it takes time for analog IPs to move to new nodes (and some may not). So what AMD did, using an advanced node for compute/logic and a less advanced one for I/Os should be typical. You can also see this in broadband cellular modems, where the baseband part is on an advanced node and the RF on an older one. When you look at processes offering, you often have variants optimized either for peak performance (frequency) or maximum efficiency. The peak performance would be the natural choice for (big) CPUs, and an efficiency node better suited for a GPU or any massively parallel accelerator where efficiency is more relevant than peak frequency (on this, I think Intel planned to use TSMC for their HPC GPU, could be related: they can focus on high perf for their CPUs).
- to11mtm 4y ago> The article notes some advantages of being able to use different processes for different wafers, but there's not much more on that. It might be helpful if you wanted different fabs for memory and compute, or for flash type memory. Anyone know what they're getting at here? Well, one advantage is that it can be a cost/efficiency savings on a few levels. For example, in the case of Zen2/3, the main CPU chiplet is at 7nm, but the I/O die is at 12nm. If I had to guess, generally speaking it is useful in cases where parts of the final module would benefit from higher transistor density versus others; Memory controller tech generally gets fewer updates than the CPU/APU itself, so it allows faster design cycles; you already know the existing I/O controller works, one less portion to re-qualify.
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- alexklarjr 4y agoNow their CPU lifespan will be same as modern videocards - 3-5 years, same as new ryzen chips. This will surely drive new products adoption and profits.
- eyegor 4y agoAre you implying that the silicon somehow has a shorter lifetime due to the presence of an interposer layer? Or is this a way of saying you think cpus are going to become more powerful at a faster rate?
- alexklarjr 4y agoBefore ryzen 3000 chiplets, CPU were everlasting, with failure rate of essentially 0 percent. AMD Ryzen 3000 chiplet failure rate was at least 5% first year and they keep degrading at astonishing speed. Like 90% of mid to high end GPUs from AMD and nvidia produced before 2016 already dead, soon you will have to thoughtfully test CPUs to understand if its condition is still acceptable. You can buy 15 years old cpu (which is 4 core 64 bit btw) and expect it to work like new.
- chupasaurus 4y agoAlright, let's use the brainpower and some history. The new Intel chips would arrive in 2023. 5 years before that Intel shipped Coffee Lake. 5 years before that Intel shipped Haswell. 5 years before that Intel shipped Yorkfield Core 2 Quads.
- alexklarjr 4y agoI have a working pentium 1 cpu, in fact ALL of them, including Z80.
- mugivarra69 4y agoLisa Su and by extention, AMD, has been ahead of anything out there. If intel can pull this off, i will be happy to have competition back in market.
- klyrs 4y agoMy understanding of the situation is that Xilinx is the real leader in multichip modules. My impression is that Intel has finally entered the race, years behind AMD, which just bought Xilinx. Probably can't even see 'em in the rear-view. But, ya know, good job Intel, you're doing great.
- pclmulqdq 4y agoAltera was also an innovator in that regard. It makes sense for Intel to buy them given that they were struggling with 3D packaging technologies before the acquisition. However, they appear to have managed Altera into the ground, and time will tell if AMD makes the same mistakes with Xilinx.
- gumby 4y agoShe is an amazing engineer and amazing ceo.
- jscipione 4y agoIntel is way behind, but at least they know it and are doing something about it. They just need to ship more 10nm processors to float them for a while so they can develop chiplets.
- TwoNineFive 4y agoThe word "AMD" is in this Intel press release once near the end, lol.