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If any chip manufacturer can hear me: please, change this metric to transistor per square millimeter. Thanks!
by marcodiego 4y ago
If any chip manufacturer can hear me: please, change this metric to transistor per square millimeter. Thanks!
- szatkus 4y agoThat wouldn't work. Transistors density depends on what you're going to build. And there are other variations between processes.
- wtmt 4y agoDo you mean transistors per cubic millimeter? Cubic centimeter (cc) may be a better choice since it’s already a more common measure of volume at smaller scales for most of the world.
- wtallis 4y agoAreal density rather than volumetric density will continue to be the most relevant basis for comparison as long as chips are still being fabricated on wafers with a fixed total area. Flash memory has been 3D for years but the important density measurement correlated to cost is still Gbit/mm^2.
- IshKebab 4y agoNo, cubic mm makes no sense because transistors are created on the surface of the wafer. It's surface area that matters. You can't get more transistors by using a thicker wafer.
- a1369209993 4y ago> You can't get more transistors by using a thicker wafer. Well, you technically can, but it's not starting with a thicker wafer, it's growing a second (or more) layer of dopable silicon on top of the normal doped silicon/transistor gate insulator/wiring/more wiring/even more wiring stack of the chip, then adding another full stack on that new dopable surface. Pretty sure the fabrication infrastructure for that makes conventional, GDP-of-a-small-country photolithography fabs look cheap by comparison, though. Plus you'd be at least squaring (and probably much worse) the already not very good production yield.
- IshKebab 4y agoYes I'm aware of Wafer on Wafer and similar technologies, but cubic mm would still be the wrong measure. Even if you stack multiple wafers or dies on top of each other you're still restricted by surface area, not volume. (Not yet anyway - I guess there might be a future where HBM gets too tall to fit in phones but we're far away from that future.)
- nomel 4y agoIs anyone doing double sided stuff yet, besides MEMs? I would assume you could dope in interconnects, between the sides.
- a1369209993 4y ago> I would assume you could dope in interconnects, between the sides. Actually, you probably can't; the distance between the sides is practically astronomical compared to the horizontal feature size. I don't remeber the exact actual dimensions, but if you assume a a 1-nm trace is equivalent to a 10-meter road, then a 1-mm wafer thickness would be equivalent a 10'000-km planetary diameter, so you're getting close to the scale of routing a internet cable through the center of the earth. (At least it's not molten, I guess?) And doping generally works by diffusion, not drilling a hole.
- snek_case 4y ago> please, change this metric to transistor per square millimeter. Thanks! I think there's problems with that metric too. Not all transistors are created equal. Depending on the switching speed that you want, how much leakage current you can tolerate, etc., I bet you can vastly change how many transistors you can fit in a given area.
- r3012 4y agoYou can actually see this for yourself in the new open source PDKs. https://skywater-pdk.readthedocs.io/en/main/contents/libraries/foundry-provided.html https://skywater-pdk.readthedocs.io/en/main/contents/librari... See how there are six foundry provided cell libraries that make different performance, power and area trade-offs. Even though it’s all 130nm. There are even more libraries than that too. Like the OSU one that makes even different trade offs.
- lizknope 4y agoI'm designing in 5nm right now and every process has multiple standard cell libraries to choose from. There is usually a high performance library and then a high density library with smaller cells. The high density library has smaller transistors but the smaller weaker devices are slower. A single chip though will have a mix of both. The high performance cells would be used in the CPU cores while the slower high density cells are used in blocks that don't need the extra speed. An example is an ethernet PHY where the device on the other end of the cable expects you to run a certain speed.
- deleted 4y ago[deleted]
- frozenport 4y agoDoes this mean you have two clock speeds on the same die?
- wtallis 4y agoEven if all parts of a die use the same transistor library, you'll still usually have lots of different clock domains so that different cores can run at different speeds according to how busy they are. And you'll sometimes have a few cores that have been identified as capable of running one or two speed bins higher than the others, from ordinary variation. But there's probably also an example of some phone chip that has Cortex A53 cores implemented on two different transistor libraries to hit significantly different performance/power points.
- exikyut 4y agoOoohh, "power" and "efficiency" cores!! AnD wItH tHe sAmE nUmBeR oF nAnOmEtErS tOo lol
- tambre 4y agoBasically all SoCs these days have plenty of different clock frequencies for different parts. Number of clock domains can easily be over a hundred.
- kergonath 4y agoThat would not solve much. Different types of transistors take different surface areas, so it would not prevent different companies using different references. Also, they can very well have a high-density library for benchmarks that can be quite different from what they can do when they actually need the thing to work. The solution is simple: treat their numbers as brands. A Core i9 is generally better than an i3 of the same generation, but where a Ryzen 5 is compared to that is anyone’s guess (depends on the exact models, generations, etc). Node sizes have had nothing to do with a characteristic length for quite a while now, that ship has sailed.
- amelius 4y agoFLOPS/mm^2 perhaps? Where 1 FLOP is a multiplication of two 128bit operands? Implemented however the foundry would like.
- kergonath 4y agoEven if it were practical, the question remains: why would they do that? The only people upset with this are benchmark warriors. People in the industry or familiar enough know how to navigate the characteristics of a process and do not need one single neat number. Customers by and large don’t care: business are after the cheapest and best supported, and consumers are mostly price-sensitive except for higher-end brands that don’t communicate at all on this sort of things. This would not solve any of the industry’s problems.
- sroussey 4y agoThey sorta have these things, but no one looks at it. For example the scaling factor from from say 5nm to 3nm for transitory is X. But for SRAM, things have been getting progressively worse so it often X/2. And with caches going up you end up using a process node terrible for sram, but needed for cpu transistors, and it’s a huge waste. You can see why you might use a different process tech for caches, and AMD is clearly going this direction. Anyhow, TMSC 3nm is just a marketing term. On the physics side, it has about 7-8 key differences to previous 5nm. That’s 6-7 too many things for people to care or remember about. Intel used to use a part of the transistor when it takes about scale. But then the geometry of the transistor changed! That number no longer has meaning. And transistor geometry changes over time, and you have multiple to choose from on the same process node. Oops. So… back to marketing terms.
- dongobongo 4y agoBetter metrics -- $/operation which includes the capital and operating cost and expected lifetime of the chip OR $/transistor or something like this.
- terafo 4y agoTSMC doesn't say that it's 3nm, they call it N3. And Intel calls their newest node(that is a bit better than N5) Intel 4.
- ebruchez 4y agoI recommend reading this article on this topic: "The node is nonsense". [1] It suggests several alternatives and is quite in depth. [1] https://read.nxtbook.com/ieee/spectrum/spectrum_na_august_2020/the_node_is_nonsense.html https://read.nxtbook.com/ieee/spectrum/spectrum_na_august_20...
- smaddox 4y agoUnfortunately, details like that are considered IP and kept secret. Sometimes there's a press release that gives some sort of metric somewhat related to density. But only when that metric happens to make that company's process look good relative to others.
- ethn 4y agoIt's a term meant for transistor manufacturers which refers to the gate length, the defining feature of the field effect transistor. It affords multiple advantages additional to more transistors per mm^2 which is merely a design choice, such as power usage.
- onedognight 4y agoHow about the square root of one over that? i.e isn’t that equivalent to what we have now?
- elif 4y agoin fairness, they did say in the article that the 3nm configuration has 1.6x the feature density of their 5nm configuration, which is arguably a more complete metric than transistor packing.
- elihu 4y agoMaybe something closer to a real-world design would be better, like "space-optimized 6502 processors per millimeter^2" or "kilobytes of SRAM per millimeter^2". Ideally you'd have some sort of metric that includes power efficiency, performance, and maybe even cost since smallness isn't really a feature in itself unless you're making something space-constrained like a hearing aid. It's hard to condense that down into a single number though.
- nomel 4y ago> like "space-optimized 6502 processors I don't think this is fair though. Some processes may support finfet, or gaffet, or some neat trick, where, if you switched to the process, but didn't optimize for size, you may be able to double the performance at half the power. Like you suggest, it's some crazy multidimensional problem space. There's no hope in representing it with one number. And, nobody that's actually designing would care about any of these numbers. In the end, they would only be used by marketing, which is all they're used for now.
- cpeterso 4y agoOr at least retcon “nm” to stand for something other than nanometers.
- mattaldisi 4y agoHey, its my first comment on Hacker News. This won't help in terms of clarity of how good the transistor is. As others mentioned, there are different kinds of transistors and different manufactures would still use their smallest (read not necessarily the fastest/strongest/mostly used) to market their process. A major reason I think this won't work is that transistor size no-longer limits the density of the chip. Nodes below 20nm have transistor contacts (what connects the silicon to metal), and metal tracks that are much larger than the transistor. The contacts typically limit the pitch between transistors and hence the density. A lot of innovation is now done to shrink those elements rather than work on the transistor physics/materials/size directly.
- croon 4y ago> A major reason I think this won't work is that transistor size no-longer limits the density of the chip. Nodes below 20nm have transistor contacts (what connects the silicon to metal), and metal tracks that are much larger than the transistor. The contacts typically limit the pitch between transistors and hence the density. A lot of innovation is now done to shrink those elements rather than work on the transistor physics/materials/size directly. Layman question from not GP, but wouldn't reducing the "overhead" around transistors increase the transistors-per-area metric and thus be at least somewhat useful?
- mattaldisi 4y agoHey, you are right. I thought about that right after I posted my comment but the devil is in the details. As you shrink the contacts and the metals their resistance and capacitance exponentially increase. This means that both your power will go up and your speeds will go down. Also the process becomes more prone to manufacturing errors. So shrinking those elements blindly without innovation just to increase the density numbers is not really a good metric of the quality of the process.
- manholio 4y agoHow about: transistor switches /( s * mm * Joule) ? Koomey's law seems to hold strong.
- deleted 4y ago[deleted]