6 ms·

Designing Billions of Circuits with Code

93 points by picture 4y ago

amelius 4y ago
Title feels wrong. It's still the developer designing those circuits. We also don't say that a compiler is designing billions of programs with code.
- kurthr 4y ago
  Well no, but the tools have definitely abstracted a huge ammount of design away from the Digital designer. Standard cells, along with standard register/RAM blocks, make Verilog(or VHDL in Europe) the only reasonable way to generate the complex systems manufactured in the latest processes (e.g. 5nm, but really anything that's not mixed signal). The EDA process flow starts with a design, which leads to code that with co-designed tests (as well as automated verification) that generates a netlist. That netlist is what gets "compiled" into silicon for a particular process... there's still moving blocks around and checking timing closure, temperature, and a zillion other things, but reverse engineering what individual transistors are doing in one of those blocks (much less what the block is doing) is pretty insane. Then after layout, there are automated Design Rule Checks and Layout Vs Schematic checks... which wouldn't really be possible, if you didn't have a very automated way of generating the schematic in the first place. At small geometries even the areas in between the wires and transistors has to be filled with just the right patterns so that lithography/etching works at those sizes. So certainly there are human developers, but they are (mostly) writing code that get's turned into working silicon... after a bunch of other less automated checks to make sure it won't break in less obvious ways.
UncleOxidant 4y ago
Having worked in EDA in the past it's kind of interesting that inside of the big 3 EDA companies (Cadence, Synopsys and Mentor Graphics) the culture seems to be very averse to change. For example, where I was working we had a C++ codebase that was mostly from the 90s. C++ templates and STL were verboten, they had their own non-templated containers from the 90s (this was in the 2006-2012 timeframe). We were using a version of gcc that was always about 7 years old. Similar for the ancient versions of RedHat we were running. Given how important EDA is to chip design you'd think there'd be more openness to innovation. The other thing that was frustrating was how siloed things were. There were software components that I'm sure other groups within the company had developed, but we were never encouraged to reach out to find out what might already be available - in fact it seemed to be discouraged. There wasn't some kind of central code repo within the company where we might look for such things - each group had their own repos that weren't accessible from outside the group. The culture had a sort of "old boys club" feel. A lot of the folks working there had been there for 15 to 20 years or more - maybe this was what contributed to that, I'm not sure. At any rate, EDA is a very interesting area to work in if you're a software engineer because there's a lot of advanced algorithmic work to do that you don't get much of working in other industries. But the way they approached that work was just not very interesting (old tools, old methodologies, etc). I suspect things are different in EDA startups, but unfortunately, they tend to be perpetually starved for cash - it's not an area that most VCs are familiar with; the time to payoff is much longer than for web startups. What tends to happen is that a startup EDA company will develop a product that falls outside of (but complementing) what's currently offered by big EDA and then they will try to get the attention of Big EDA and get bought by one of the Big 3 - that's the measure of success, not going public as would be in other industries because it's been extremely rare for EDA startups to go public since the big 3 have become established.
- shadowgovt 4y ago
  > Given how important EDA is to chip design you'd think there'd be more openness to innovation. Hypothesis: the importance of EDA to chip design makes it change-averse. I once had to chase down a delta between two triangle mesh files that resulted from two different builds of the same compiler, running on two slightly different hardware configurations, compiling the same source into different floating-point code that calculated a result of -0 instead of 0, which resulted in a no-difference rotation on the indices of every vertex on every triangle in the entire file. Given that it's basically impossible to mathematically validate C++ code, if any change could cause a difference in output in a million-transistor layout, how would an engineer confirm that difference didn't matter? That kind of problem drives the cost way up for changes to the codebase.
- rathel 4y ago
  Rest assured that one of the companies you mentioned has deployed a catalog of reusable software components not long ago. It's already quite populated. But the funny thing is, you need VP approval to submit your modules. I agree that EDA companies are unnecessarily siloed and dated in many places. Weren't it for the moat of hundreds of PhD's working on the algorithms, it'd have been disrupted to hell by startups.
  - UncleOxidant 4y ago
    > Rest assured that one of the companies you mentioned has deployed a catalog of reusable software components not long ago. It's already quite populated. But the funny thing is, you need VP approval to submit your modules. LoL this seems par for the course.
  - InitialLastName 4y ago
    EDA software provides the infrastructure for projects with very high NRE and with low tolerance for failure (you can't just recompile and deploy a new chip design for free when you've already built a million bricks). Their entire business model is built around risk avoidance, so it would require an enormous improvement in efficiency for a client to take a risk on a "disrupting" startup's tools.
Taniwha 4y ago
I would take this article with a grain of salt - especially the whole "logic designers do X and then physical designers do Y" bit. My experience doing this has physical designers working on cell libraries in parallel with logic designers working on designs, then both working on layout and then the physical designers leading the final tapeout - logic designers need those cell library timings early on to drive synthesis
- tyrfing 4y ago
  That would be DTCO, right? As far as semi blogs go, this does seem extremely high level. Not sure I've seen a good writeup of EDA yet though.
  - Taniwha 4y ago
    not formally, just people working to get stuff done - as a nominal 'logic designer' I've routed my blocks, written scan insertion software, done back end static timing closure etc etc There's just a lot of scope for the physical designers and logic designers to work together ("we really need a cell that does X"/"this cell doesn't route well, I want to remove it") to produce good results
jeanlucas 4y ago
Nice to see asianometry being shared here
lizknope 4y ago
I've been in digital physical design for 25 years. The Asianometry videos are a good intro into some of this. On the analog side you have a lot of custom transistors and hand drawn layout. On the digital side it is Verilog RTL, synthesis to logic gates, and automated place and route. The CAD flow is literally tens of thousands of lines of Tcl code gluing tools hundreds of libraries and tools from multiple vendors into something that just crashes once a day and not constantly. There is still a lot of manual work involved even on the digital side. The number of PVT (Process / Voltage / Temperature) timing corners has exploded over the last decade. The design can have no logical bugs and timing closure still takes 6 months on big chips. Hundreds of clocks, new DRC violation types with every new process shrink. More tools to check IR drop, electromigration, yield enhancement. One engineer is able to do something that would have taken 25 engineers 25 years ago but the chips have grown in size and complexity. We have over 50 physical design engineers on my current 20x20mm 5nm chip. Probably another 50 RTL designers, 10 DFT, an army of verification engineers. I'm ignoring the lab debug and software teams which I don't know as much about. Designing with code is the only way to realistically do this on the schedules we have which are usually 1.5 to 2 years.
- gautamcgoel 4y ago
  What kind of chip are you guys building?
  - lizknope 4y ago
    Large networking chip
- pbazarnik 4y ago
  At deep submicron technologies even analog circuit layout must be done by CAD tool in order to meet DFM (design for manufacturing ) rules. These rules (due to interference effects used in photolitography) are too complex for manual layout of even medium size designs within reasonable schedule. Manual layout results in lingering rule viloations and larger utilized silicone area than CAD tool output.
  - 4y ago

93 points by picture 4y ago

Title feels wrong. It's still the developer designing those circuits. We also don't say that a compiler is designing billions of programs with code.

kurthr 4y ago
Well no, but the tools have definitely abstracted a huge ammount of design away from the Digital designer. Standard cells, along with standard register/RAM blocks, make Verilog(or VHDL in Europe) the only reasonable way to generate the complex systems manufactured in the latest processes (e.g. 5nm, but really anything that's not mixed signal). The EDA process flow starts with a design, which leads to code that with co-designed tests (as well as automated verification) that generates a netlist. That netlist is what gets "compiled" into silicon for a particular process... there's still moving blocks around and checking timing closure, temperature, and a zillion other things, but reverse engineering what individual transistors are doing in one of those blocks (much less what the block is doing) is pretty insane. Then after layout, there are automated Design Rule Checks and Layout Vs Schematic checks... which wouldn't really be possible, if you didn't have a very automated way of generating the schematic in the first place. At small geometries even the areas in between the wires and transistors has to be filled with just the right patterns so that lithography/etching works at those sizes. So certainly there are human developers, but they are (mostly) writing code that get's turned into working silicon... after a bunch of other less automated checks to make sure it won't break in less obvious ways.

UncleOxidant 4y ago

Having worked in EDA in the past it's kind of interesting that inside of the big 3 EDA companies (Cadence, Synopsys and Mentor Graphics) the culture seems to be very averse to change. For example, where I was working we had a C++ codebase that was mostly from the 90s. C++ templates and STL were verboten, they had their own non-templated containers from the 90s (this was in the 2006-2012 timeframe). We were using a version of gcc that was always about 7 years old. Similar for the ancient versions of RedHat we were running. Given how important EDA is to chip design you'd think there'd be more openness to innovation. The other thing that was frustrating was how siloed things were. There were software components that I'm sure other groups within the company had developed, but we were never encouraged to reach out to find out what might already be available - in fact it seemed to be discouraged. There wasn't some kind of central code repo within the company where we might look for such things - each group had their own repos that weren't accessible from outside the group. The culture had a sort of "old boys club" feel. A lot of the folks working there had been there for 15 to 20 years or more - maybe this was what contributed to that, I'm not sure. At any rate, EDA is a very interesting area to work in if you're a software engineer because there's a lot of advanced algorithmic work to do that you don't get much of working in other industries. But the way they approached that work was just not very interesting (old tools, old methodologies, etc). I suspect things are different in EDA startups, but unfortunately, they tend to be perpetually starved for cash - it's not an area that most VCs are familiar with; the time to payoff is much longer than for web startups. What tends to happen is that a startup EDA company will develop a product that falls outside of (but complementing) what's currently offered by big EDA and then they will try to get the attention of Big EDA and get bought by one of the Big 3 - that's the measure of success, not going public as would be in other industries because it's been extremely rare for EDA startups to go public since the big 3 have become established.

shadowgovt 4y ago
> Given how important EDA is to chip design you'd think there'd be more openness to innovation. Hypothesis: the importance of EDA to chip design makes it change-averse. I once had to chase down a delta between two triangle mesh files that resulted from two different builds of the same compiler, running on two slightly different hardware configurations, compiling the same source into different floating-point code that calculated a result of -0 instead of 0, which resulted in a no-difference rotation on the indices of every vertex on every triangle in the entire file. Given that it's basically impossible to mathematically validate C++ code, if any change could cause a difference in output in a million-transistor layout, how would an engineer confirm that difference didn't matter? That kind of problem drives the cost way up for changes to the codebase.
rathel 4y ago
Rest assured that one of the companies you mentioned has deployed a catalog of reusable software components not long ago. It's already quite populated. But the funny thing is, you need VP approval to submit your modules. I agree that EDA companies are unnecessarily siloed and dated in many places. Weren't it for the moat of hundreds of PhD's working on the algorithms, it'd have been disrupted to hell by startups.
- UncleOxidant 4y ago
  > Rest assured that one of the companies you mentioned has deployed a catalog of reusable software components not long ago. It's already quite populated. But the funny thing is, you need VP approval to submit your modules. LoL this seems par for the course.
- InitialLastName 4y ago
  EDA software provides the infrastructure for projects with very high NRE and with low tolerance for failure (you can't just recompile and deploy a new chip design for free when you've already built a million bricks). Their entire business model is built around risk avoidance, so it would require an enormous improvement in efficiency for a client to take a risk on a "disrupting" startup's tools.

Taniwha 4y ago

I would take this article with a grain of salt - especially the whole "logic designers do X and then physical designers do Y" bit. My experience doing this has physical designers working on cell libraries in parallel with logic designers working on designs, then both working on layout and then the physical designers leading the final tapeout - logic designers need those cell library timings early on to drive synthesis

tyrfing 4y ago
That would be DTCO, right? As far as semi blogs go, this does seem extremely high level. Not sure I've seen a good writeup of EDA yet though.
- Taniwha 4y ago
  not formally, just people working to get stuff done - as a nominal 'logic designer' I've routed my blocks, written scan insertion software, done back end static timing closure etc etc There's just a lot of scope for the physical designers and logic designers to work together ("we really need a cell that does X"/"this cell doesn't route well, I want to remove it") to produce good results

jeanlucas 4y ago

Nice to see asianometry being shared here

lizknope 4y ago

I've been in digital physical design for 25 years. The Asianometry videos are a good intro into some of this. On the analog side you have a lot of custom transistors and hand drawn layout. On the digital side it is Verilog RTL, synthesis to logic gates, and automated place and route. The CAD flow is literally tens of thousands of lines of Tcl code gluing tools hundreds of libraries and tools from multiple vendors into something that just crashes once a day and not constantly. There is still a lot of manual work involved even on the digital side. The number of PVT (Process / Voltage / Temperature) timing corners has exploded over the last decade. The design can have no logical bugs and timing closure still takes 6 months on big chips. Hundreds of clocks, new DRC violation types with every new process shrink. More tools to check IR drop, electromigration, yield enhancement. One engineer is able to do something that would have taken 25 engineers 25 years ago but the chips have grown in size and complexity. We have over 50 physical design engineers on my current 20x20mm 5nm chip. Probably another 50 RTL designers, 10 DFT, an army of verification engineers. I'm ignoring the lab debug and software teams which I don't know as much about. Designing with code is the only way to realistically do this on the schedules we have which are usually 1.5 to 2 years.

gautamcgoel 4y ago
What kind of chip are you guys building?
- lizknope 4y ago
  Large networking chip
pbazarnik 4y ago
At deep submicron technologies even analog circuit layout must be done by CAD tool in order to meet DFM (design for manufacturing ) rules. These rules (due to interference effects used in photolitography) are too complex for manual layout of even medium size designs within reasonable schedule. Manual layout results in lingering rule viloations and larger utilized silicone area than CAD tool output.
- 4y ago