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https://threadreaderapp.com/thread/1514295682777059329.html https://threadreaderapp.com/thread/1514295682777059329.html The tweets refer to Tile-Based Deferred

by sounds 5y ago

https://threadreaderapp.com/thread/1514295682777059329.html https://threadreaderapp.com/thread/1514295682777059329.html The tweets refer to Tile-Based Deferred Rendering (TBDR) [1] as compared to Tile-Based Immediate Rendering (TBIR). Here's another take on it: https://docs.imgtec.com/Architecture_Guides/PowerVR_Architecture/topics/powervr_architecture_tile_based_deferred_rendering__tbdr.html https://docs.imgtec.com/Architecture_Guides/PowerVR_Architec... Note that TBIR appears to be a term the author just made up to refer to apps that have not be specifically optimized for the Apple M1 Ultra GPU architecture. [1] https://developer.apple.com/documentation/metal/resource_fundamentals/understanding_gpu_family_4 https://developer.apple.com/documentation/metal/resource_fun...

ksec 5y ago
>Note that TBIR appears to be a term the author... Tile-Based Immediate Rendering, or Tile-based immediate mode rendering (TBIM) is quite well known and not an invented term. [1] Given this is from MaxTech. I nearly stopped reading when he listed "they started working on the chips 5-7 years ago". But since he quoted hishnash, may be worth a read anyway. I also doubt the the so called GPU limitation is due to this. The GPU TDP usage depends on a lot of other factors. This TBDR limitation, if you can call it that has been well known since PowerVR / Dreamcast's days ( Someone please make a low cost Super-H Chip ). Most of the explanation seems very weird from a cache and memory access perspective. And as @lamchester pointed out later [2], a lot of it doesn't make any sense. And remember, M1 Ultra is two M1 Max. Which means there are many some small details missing in how it works together. [1] https://en.wikipedia.org/wiki/Tiled_rendering https://en.wikipedia.org/wiki/Tiled_rendering [2] https://twitter.com/lamchester/status/1514346083819786240 https://twitter.com/lamchester/status/1514346083819786240
- vvanders 5y ago
  I've never heard it called TBIR, always TBDR or just tile based rendering. I honestly can't make heads or tails of the Twitter thread. It talks about having too many small reads/writes but that's the whole point of tile based rendering. You use the tile as scratch space to do operations that are expensive in system memory. This approach is well over a decade old at this point and pretty ubiquitous in power constrained rendering scenarios[1]. Best I can tell you need to take architecture into consideration when trying to get the peak GPU usage which has always been true of any platform regardless of tiled or immediate mode rendering. [1] https://developer.qualcomm.com/sites/default/files/docs/adreno-gpu/developer-guide/gpu/overview.html#tile-based-rendering https://developer.qualcomm.com/sites/default/files/docs/adre...
  - brigade 5y ago
    Accessing tile memory doesn't need an address translation; it's not part of virtual memory. Accessing global memory does. I think the claim is that the typical working set can exceed what the TLB can map once the GPU scales to 32 or more cores, so the TLB starts thrashing. Optimizing for TBDR would alleviate this because all the tile memory accesses would bypass the TLB, and also likely reduce the working set because the intermediate buffers don't need VM mapping.
    - vvanders 5y ago
      Yeah but a TLB is for user space virtual memory mapping. When your talking about GPU operations those usually go through opaque handles or allocated buffers and the DMA/read/write is done outside of user space(aside from initial data uploads or the case where you have unsynchronized user space memory buffers, but that's not usually the norm). Some of this changes a bit with Vulkan but it's not really clear from the thread how a TLB fits in. Optimizing for TBR involves reducing drawcalls, buffer target switches and operations that are orthogonal to what a TLB historically does.
      - brigade 5y ago
        ...there are modern integrated GPUs that don't use virtual memory for all global resources? I expected that was a given to even just have an MMU enforce security when accessing RAM.
        vvanders 5y ago
        I'm not privy to the security mechanisms of the integrated GPUs I've worked with however I've got a decent amount of experience with mostly tile based GPUs and I've never hit TLB misses as a reason the GPU is going slow. On the CPU? Sure, but unless they want to get a lot more specific on what these optimizations are it's a bit hard to piece together what's going on here. GPUs don't like to read around in memory(neither do CPUs for that matter but then tend to branch and be a lot less predictable) so optimizing reads/writes are something you will do regardless. The painful parts of TBRs usually(but not universally) have to do with drawcalls setup and render target switching. I remember some of the early iPhones had pretty painfully low drawcalls limits associated with the overhead with dispatching the actual calls as opposed to triangle count or fillrate. It's fairly easy to put together the synthetic benchmarks to shake that out.
- jayd16 5y ago
  What is TBIM? Is it a tile based render that doesn't bother rejecting fully occluded geometry? If not, what is it?
- MBCook 5y ago
  > MaxTech Is he popular? I’ve only run across his videos once or twice but I get the feeling our estimations of his technical knowledge match.
  - Dave_Rosenthal 5y ago
    Yes, he is popular. Yes, he loves click bait. No, he does not have a deep understanding of technical subject matter. All that said, as a journalist he seem to genuinely try hard to get to the bottom of technical issues relating to Apple and report on them.
    - jhugo 5y ago
      "Journalist" might be a bit strong? He is clearly pretending to have a much deeper understanding of the subject than he does, meanwhile throwing around accusations of design flaws...
      - freemint 5y ago
        Bigger Cache would help GPU Apps which are not optimized for a tile based approach perform better. That this becomes a constraint on the Ultra and some apps some to suffer worse scaling on the Ultra the other products in the line seems reproducible though.
- freemint 5y ago
  You can make your own low-cost SuperH as SuperH patents (but not brand name) have expired. If you are interested write to the j-core mailing list with what kind of chips (is it more micro controller or older mobile class chip) you are interested in and see if they have a chip already that suites that need. If the people behind J-Core ever print silicon they surely won't mind printing and packaging in larger numbers and sell some as part of the batch.

by sounds 5y ago

ksec 5y ago

>Note that TBIR appears to be a term the author... Tile-Based Immediate Rendering, or Tile-based immediate mode rendering (TBIM) is quite well known and not an invented term. [1] Given this is from MaxTech. I nearly stopped reading when he listed "they started working on the chips 5-7 years ago". But since he quoted hishnash, may be worth a read anyway. I also doubt the the so called GPU limitation is due to this. The GPU TDP usage depends on a lot of other factors. This TBDR limitation, if you can call it that has been well known since PowerVR / Dreamcast's days ( Someone please make a low cost Super-H Chip ). Most of the explanation seems very weird from a cache and memory access perspective. And as @lamchester pointed out later [2], a lot of it doesn't make any sense. And remember, M1 Ultra is two M1 Max. Which means there are many some small details missing in how it works together. [1] https://en.wikipedia.org/wiki/Tiled_rendering https://en.wikipedia.org/wiki/Tiled_rendering [2] https://twitter.com/lamchester/status/1514346083819786240 https://twitter.com/lamchester/status/1514346083819786240

vvanders 5y ago
I've never heard it called TBIR, always TBDR or just tile based rendering. I honestly can't make heads or tails of the Twitter thread. It talks about having too many small reads/writes but that's the whole point of tile based rendering. You use the tile as scratch space to do operations that are expensive in system memory. This approach is well over a decade old at this point and pretty ubiquitous in power constrained rendering scenarios[1]. Best I can tell you need to take architecture into consideration when trying to get the peak GPU usage which has always been true of any platform regardless of tiled or immediate mode rendering. [1] https://developer.qualcomm.com/sites/default/files/docs/adreno-gpu/developer-guide/gpu/overview.html#tile-based-rendering https://developer.qualcomm.com/sites/default/files/docs/adre...
- brigade 5y ago
  Accessing tile memory doesn't need an address translation; it's not part of virtual memory. Accessing global memory does. I think the claim is that the typical working set can exceed what the TLB can map once the GPU scales to 32 or more cores, so the TLB starts thrashing. Optimizing for TBDR would alleviate this because all the tile memory accesses would bypass the TLB, and also likely reduce the working set because the intermediate buffers don't need VM mapping.
  - vvanders 5y ago
    Yeah but a TLB is for user space virtual memory mapping. When your talking about GPU operations those usually go through opaque handles or allocated buffers and the DMA/read/write is done outside of user space(aside from initial data uploads or the case where you have unsynchronized user space memory buffers, but that's not usually the norm). Some of this changes a bit with Vulkan but it's not really clear from the thread how a TLB fits in. Optimizing for TBR involves reducing drawcalls, buffer target switches and operations that are orthogonal to what a TLB historically does.
    - brigade 5y ago
      ...there are modern integrated GPUs that don't use virtual memory for all global resources? I expected that was a given to even just have an MMU enforce security when accessing RAM.
      - vvanders 5y ago
        I'm not privy to the security mechanisms of the integrated GPUs I've worked with however I've got a decent amount of experience with mostly tile based GPUs and I've never hit TLB misses as a reason the GPU is going slow. On the CPU? Sure, but unless they want to get a lot more specific on what these optimizations are it's a bit hard to piece together what's going on here. GPUs don't like to read around in memory(neither do CPUs for that matter but then tend to branch and be a lot less predictable) so optimizing reads/writes are something you will do regardless. The painful parts of TBRs usually(but not universally) have to do with drawcalls setup and render target switching. I remember some of the early iPhones had pretty painfully low drawcalls limits associated with the overhead with dispatching the actual calls as opposed to triangle count or fillrate. It's fairly easy to put together the synthetic benchmarks to shake that out.
jayd16 5y ago
What is TBIM? Is it a tile based render that doesn't bother rejecting fully occluded geometry? If not, what is it?
MBCook 5y ago
> MaxTech Is he popular? I’ve only run across his videos once or twice but I get the feeling our estimations of his technical knowledge match.
- Dave_Rosenthal 5y ago
  Yes, he is popular. Yes, he loves click bait. No, he does not have a deep understanding of technical subject matter. All that said, as a journalist he seem to genuinely try hard to get to the bottom of technical issues relating to Apple and report on them.
  - jhugo 5y ago
    "Journalist" might be a bit strong? He is clearly pretending to have a much deeper understanding of the subject than he does, meanwhile throwing around accusations of design flaws...
    - freemint 5y ago
      Bigger Cache would help GPU Apps which are not optimized for a tile based approach perform better. That this becomes a constraint on the Ultra and some apps some to suffer worse scaling on the Ultra the other products in the line seems reproducible though.
freemint 5y ago
You can make your own low-cost SuperH as SuperH patents (but not brand name) have expired. If you are interested write to the j-core mailing list with what kind of chips (is it more micro controller or older mobile class chip) you are interested in and see if they have a chip already that suites that need. If the people behind J-Core ever print silicon they surely won't mind printing and packaging in larger numbers and sell some as part of the batch.