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The Load Balancer is there because the M1 Max has two independent Neural Engines (unlike the GPU cores, which are load balanced in hardware and the OS sees as a

The Load Balancer is there because the M1 Max has two independent Neural Engines (unlike the GPU cores, which are load balanced in hardware and the OS sees as a single one even on the Ultra)... but one ANE is inexplicably disabled on all production systems. The M1 Ultra, logically, has four... and only the first in each die is enabled. I was waiting for the Mac Studio to drop to come to a conclusion, since it's plausible one ANE could've been disabled for power reasons on the laptops... but with both secondary ANEs in each die in the M1 Ultra off, and with no reports of anyone seeing the first ANE being disabled instead (which could mean it's a yield thing), I'm going to go ahead and say there was a silicon bug or other issue that made the second ANE inoperable or problematic, and they just decided to fuse it off and leave it as dead silicon on all M1 Max/Ultra systems.

erwincoumans 4y ago
That is interesting, do you have any references / articles that describe that some ANE's are disabled? Could it be overheating if the ANE's are not used the right way?
- Jcowell 4y ago
  Probably not but he’s the one the highest divers into the M1 Chip due to his Linux Project so he’s probably the reputable source. Any article written would probably be referencing him.
  - erwincoumans 4y ago
    Ah, delightful to have a/the master behind Asahi development/reverse engineering efforts here!
    - bschwindHN 4y ago
      Delightful to see the creator of Bullet Physics here in the comments too!
bayindirh 4y ago
Maybe they want to push one as further as possible before enabling the other, hence seeing the limits and increasing the life of the systems by forcing developers to optimize their code? Sony pulled a similar trick on their A7 series cameras, and enabled more advanced AF features just with a firmware upgrade. It made the bodies "new" and pushed them at least half a generation forward. It's not the same thing, I know, but it feels similar enough for me.
- AgentOrange1234 4y ago
  Another possible reason would be that there’s a hardware bug which only occurs when both are enabled. (Not saying this is what’s happening here, but it’s very common to ship partly disabled chips to work around bugs.)
  - vatys 4y ago
    For chips, that's commonly referred to as "binning" as in the sorting machine drops chips into different bins based on a test result. A big design with many cores, such as CPU or GPU cores, may have manufacturing defects that makes one or more cores bad. Or it may be on one side or another of a tolerance range and not be able to work at higher power or higher frequency. These parts may get "binned" into a lower performance category, with some cores disabled (because a flaw prevents the core from working) or with reduced maximum performance states. These are still "good" parts, and can be sold at a lower cost with lower performance, while the "better" and "best" parts will pass more tests and be able to have more or all portions of the chip enabled. So it's not so much to work around a "bug" which might be a common flaw to all part designs, rather to work around manufacturing tolerance and allow more built parts to be useful rather than garbage.
    - brigade 4y ago
      Manufacturing defects are not hardware bugs. Binning is irrelevant to hardware bugs.
      - 4y ago
greggsy 4y ago
Perhaps they’ll allow you to use it through subscription, like z/OS mainframes locking down cores?
grishka 4y ago
Is the second ANE disabled in hardware or is it possible to reenable it through software somehow?
- exikyut 4y ago
  Just make sure there are no SkyNet singularities hiding inside first. ...maybe Apple disabled it for a reason, y'know?
  - thisNeeds2BeSad 4y ago
    Maybe protect against lawsuits from a chip patch slowdown after architectural migations are necessary, because of inherent design speed optimization safety flaws?
- marcan_42 4y ago
  It's disabled and locked in boot firmware, and the firmware is signed.
  - unicornfinder 4y ago
    Which implies that, at least theoretically, that Apple could enable the other neural engine at a later date (not that they would).
dannyw 4y ago
It's just an yields thing I bet; particularly given the relative lack of usage of Neural Engine. If Apple engineers realize that, disabling half the Neural Engines makes no user-visible difference and improves yields by ~1% (hence decreasing silicon costs by ~1%), that's an easy hundreds of millions in saved wafers.
- ricardobeat 4y ago
  Doesn’t the fact that it’s always the first chip that gets disabled disprove that theory? If it was to improve yield you’d see the other one being disabled at least some of the time.
  - fredoralive 4y ago
    It probably depends on the chip yield, and the sample size of whatever survey was used for the assertion it was always the second engine disabled. It would be reasonable to assume that if both engines work, then the second is always the one to be disabled. Therefore to have the second enabled you'd need to find one where the first engine has failed, and has no other chip killing faults. Depending on the yield TSMC gets, these could be quite rare, so you'd have to have quite a large survey to find them. Or as other people have noted, it could be an errata meaning the second core is broken, as this isn't the only possible reason.
    - WithinReason 4y ago
      This would be a reasonable theory, except the neural engine is a small part of the total chip area and thus unlikely to contribute significantly to total chip yield
    - marcan_42 4y ago
      I know it's not the largest sample size, but I did ask twitter and nobody found one with ane1 enabled, it's always ane0.
IshKebab 4y ago
My guess would be either a power consumption issue - with both ANEs enabled you could get voltage droops below the acceptable limit. Or it requires software support that they haven't implemented yet. Software always takes waaaay longer than hardware people expect.
- marcan_42 4y ago
  They sold the chips as having only on me ANE, and software support is there since it's used in the M1 Ultra...
runnerup 4y ago
> it's plausible one ANE could've been disabled for power reasons on the laptops The linked posting notes that they were able to get the ANE to draw 49 mW. Is this such a significant amount of power that its worth permanently disabling for laptop power draw? Or is there likely much more power being used elsewhere to support ANE in addition to the 49 mW that can be measured directly?

erwincoumans 4y ago

That is interesting, do you have any references / articles that describe that some ANE's are disabled? Could it be overheating if the ANE's are not used the right way?

Jcowell 4y ago
Probably not but he’s the one the highest divers into the M1 Chip due to his Linux Project so he’s probably the reputable source. Any article written would probably be referencing him.
- erwincoumans 4y ago
  Ah, delightful to have a/the master behind Asahi development/reverse engineering efforts here!
  - bschwindHN 4y ago
    Delightful to see the creator of Bullet Physics here in the comments too!

bayindirh 4y ago

Maybe they want to push one as further as possible before enabling the other, hence seeing the limits and increasing the life of the systems by forcing developers to optimize their code? Sony pulled a similar trick on their A7 series cameras, and enabled more advanced AF features just with a firmware upgrade. It made the bodies "new" and pushed them at least half a generation forward. It's not the same thing, I know, but it feels similar enough for me.

AgentOrange1234 4y ago
Another possible reason would be that there’s a hardware bug which only occurs when both are enabled. (Not saying this is what’s happening here, but it’s very common to ship partly disabled chips to work around bugs.)
- vatys 4y ago
  For chips, that's commonly referred to as "binning" as in the sorting machine drops chips into different bins based on a test result. A big design with many cores, such as CPU or GPU cores, may have manufacturing defects that makes one or more cores bad. Or it may be on one side or another of a tolerance range and not be able to work at higher power or higher frequency. These parts may get "binned" into a lower performance category, with some cores disabled (because a flaw prevents the core from working) or with reduced maximum performance states. These are still "good" parts, and can be sold at a lower cost with lower performance, while the "better" and "best" parts will pass more tests and be able to have more or all portions of the chip enabled. So it's not so much to work around a "bug" which might be a common flaw to all part designs, rather to work around manufacturing tolerance and allow more built parts to be useful rather than garbage.
  - brigade 4y ago
    Manufacturing defects are not hardware bugs. Binning is irrelevant to hardware bugs.
    - 4y ago

greggsy 4y ago

Perhaps they’ll allow you to use it through subscription, like z/OS mainframes locking down cores?

grishka 4y ago

Is the second ANE disabled in hardware or is it possible to reenable it through software somehow?

exikyut 4y ago
Just make sure there are no SkyNet singularities hiding inside first. ...maybe Apple disabled it for a reason, y'know?
- thisNeeds2BeSad 4y ago
  Maybe protect against lawsuits from a chip patch slowdown after architectural migations are necessary, because of inherent design speed optimization safety flaws?
marcan_42 4y ago
It's disabled and locked in boot firmware, and the firmware is signed.
- unicornfinder 4y ago
  Which implies that, at least theoretically, that Apple could enable the other neural engine at a later date (not that they would).

dannyw 4y ago

It's just an yields thing I bet; particularly given the relative lack of usage of Neural Engine. If Apple engineers realize that, disabling half the Neural Engines makes no user-visible difference and improves yields by ~1% (hence decreasing silicon costs by ~1%), that's an easy hundreds of millions in saved wafers.

ricardobeat 4y ago
Doesn’t the fact that it’s always the first chip that gets disabled disprove that theory? If it was to improve yield you’d see the other one being disabled at least some of the time.
- fredoralive 4y ago
  It probably depends on the chip yield, and the sample size of whatever survey was used for the assertion it was always the second engine disabled. It would be reasonable to assume that if both engines work, then the second is always the one to be disabled. Therefore to have the second enabled you'd need to find one where the first engine has failed, and has no other chip killing faults. Depending on the yield TSMC gets, these could be quite rare, so you'd have to have quite a large survey to find them. Or as other people have noted, it could be an errata meaning the second core is broken, as this isn't the only possible reason.
  - WithinReason 4y ago
    This would be a reasonable theory, except the neural engine is a small part of the total chip area and thus unlikely to contribute significantly to total chip yield
  - marcan_42 4y ago
    I know it's not the largest sample size, but I did ask twitter and nobody found one with ane1 enabled, it's always ane0.

IshKebab 4y ago

My guess would be either a power consumption issue - with both ANEs enabled you could get voltage droops below the acceptable limit. Or it requires software support that they haven't implemented yet. Software always takes waaaay longer than hardware people expect.

marcan_42 4y ago
They sold the chips as having only on me ANE, and software support is there since it's used in the M1 Ultra...

runnerup 4y ago

> it's plausible one ANE could've been disabled for power reasons on the laptops The linked posting notes that they were able to get the ANE to draw 49 mW. Is this such a significant amount of power that its worth permanently disabling for laptop power draw? Or is there likely much more power being used elsewhere to support ANE in addition to the 49 mW that can be measured directly?